IITC panel: Moore’s Wall still elusive

by Ed Korczynski, senior technical editor, Solid State Technology

June 3, 2008 – Chris Malachowsky, co-founder, fellow, and SVP of operations of NVidia, gave a great perspective on the motivation for continuing the classic Moore’s Law scaling trend for logic in an IITC evening panel discussion sponsored by Applied Materials.

He first explained the generations of graphics processing, starting with simple wireframe modeling of thousands of nodes, moving through a 2nd-generation phase of polygon modeling (1987-1992), to a 3rd-gen of texture mapping (1992-2000), and into the current generation of programmability in the chips, which allows for an instruction set to render things based on other images in the virtual space.

Over just the last seven years, Malachowsky noted, NVidia’s leading GPU chips have evolved as follows: 150/140nm to 65/55nm node processing, ~23× increase in transistors (~600M to 1.4B), ~2.6× increase in I/O (420 to 1100), ~22× increase in internal memory, ~4× increase in die size, and ~6× increase in design rule constraints.

Today’s 4th-generation GPUs are now used by the national weather service for predictions, by oil companies for exploration, and many other applications beyond games. “We’re at the beginning of a new computer revolution. The most personal computer is about to be something you carry with you,” said Malachowsky.

The 5th-gen under development is “visual computing” based on ray tracing (visibility and integration), true shadows, path tracing, photon mapping, and heterogeneous computing (using 1.4 billion transistors set up as hundreds of cores). — E.K.

Logic Node………….Interconnect pitch


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