by Ed Korczynski, senior technical editor, Solid State Technology
The 11th International Interconnect Technology Conference (IITC) is now underway in Burlingame, CA, once again presenting the leading-edge of on-chip interconnect technology developments, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) are being discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes along with new copper barrier materials.
3D with TSV may be the ultimate interconnect concept, since stacked chips provide optimal functionality/volume and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV (and many variations thereof) have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, "via-first" TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, "3D is such a 'silicon-centric' process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here."