IMEC, Aixtron tout low-power GaN “milestone”

June 3, 2008 – European R&D consortium IMEC and Aixtron say they achieved a “milestone” of growing AlGaN/GaN heterostructures on 200mm silicon wafers, a step toward fabricating low-cost GaN power devices for high-efficiency/high-power systems beyond silicon limits.

The standard layer stack had already been demonstrated with 100mm and 150mm Si (111) substrates — 150mm and 200mm are seen as the starting points to fully realize silicon processing capabilities for GaN devices. MEMC supplied the custom-made (Czochralski growth) 200m Si wafers.

GaN, which offers benefits in terms of power, low-noise, high-frequency, high-temperature operations (including harsh environments e.g. radiation), typically is grown on sapphire and silicon carbide (SiC), but silicon is a much cheaper alternative, with better thermal conductivity (half that of SiC) and more extensive supplies. Part of the teams’ progress has been aided by newly available (111) Si wafers with up to 150mm diameters, they note.

“There is a strong demand for GaN-based solid-state switching devices in the field of power conversion,” said Marianne Germain, program manager of IMEC’s Efficient Power program, in a statement. “However, bringing GaN devices to a level acceptable for most applications requires a drastic reduction in the cost of this technology. And that is only possible by processing on large-diameter Si wafers.”

The researchers say the deposited crack-free AlGaN/GaN structures onto 200mm Si (111) wafers show “good crystalline quality” (measured by x-ray diffraction), with “excellent morphology and uniformity.” The AlGaN and GaN layers were grown in Aixtron’s application labs on its 300mm MOCVD epitaxy reactor.

Specific process details were as follows, according to the firms in a statement:

– An AlN layer deposited onto the Si substrate;
– Followed by an AlGaN buffer to provide compressive stress in the 1μm GaN top layer;
– Topped with a 20nm AlGaN (26% Al) layer;
– and capped with a 2nm GaN layer.

In-situ measurements showed thickness uniformity of standard deviation “well below 1%” over the full wafer (5mm EE). The bow of the bigger wafers is still “quite large” (~100μm) but should be able to be reduced through an optimize buffer, and eventually the wafers will be qualified as Si-CMOS process compatible, according to Germain.

Thickness uniformity map of a 1μm GaN layer deposited on 200mm Si(111) using an AlN/AlGaN buffer. Average thickness measured in-situ is 1008nm (σ = 0.5%) for the full wafer, excluding a 5mm edge. (Source: IMEC)


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