Intel eyes scalable FBC technology for 15nm and beyond

By James Montgomery, News Editor, and Debra Vogler, Senior Technical Editor, Solid State Technology

June 17, 2008 – Among the papers being presented by Intel at the VLSI Symposium (June 17-20 in Hawaii) is one describing fabrication of the smallest reported floating body cell (FBC) planar devices, with functional devices measuring down to 30nm gate length (#9.4, “A Scaled Floating Body Cell Memory with High-k + Metal Gate on Thin-Silicon and Thin-BOX for 15nm Node and Beyond”). FBC memories are potentially more dense than a conventional cache memory that uses six transistors, whereas an FBC memory uses only one. There is some overhead required to make it work, so the density benefit is expected to be ~3-4× better in bits/area for a given generation.

“FBC is a candidate for increased memory density compared to the standard six transistor cache memory that is used in all microprocessors today,” said Mike Mayberry, VP of Intel’s technology & manufacturing group and director of component research. He said that memories based on the technology potentially would be less costly than embedded DRAM because a special capacitor isn’t required (i.e., the capacitor is in the body of the cell). More bits within a given die area translates to faster computation.

This most recent FBC device (see Figure) is planar on very thin SOI, where the silicon layer is 22nm thick, and the buried oxide layer is 10nm thick. The thin buried oxide layer allows the use of lower voltage than currently needed on most other SOI-based devices. Intel says it has made cells down to a 30nm gate length, which translates to a cell size of 0.01μm2 or less — that’s more than a factor of 30× smaller than the size of the cache memory on the 45nm node Intel is shipping today.

Intel also said it was able to achieve good retention results for the devices with 60nm gate lengths, and has obtained excellent agreement between simulation and experiments. The current work is at the single cell level, so the next step is building a larger array to assess process variability, which may ultimately limit the scaling of the technology. Though no decision has been made on a product intercept for this FBC technology, Mayberry said that it is conceivable for the 16nm node or beyond.

Asked during the presentation Q&A about extra manufacturing steps or hurdles with the new FBC cells, Mayberry indicated that lithography is not a challenge because it’s not different from what Intel currently uses at 45nm (implying 193nm dry litho). However, integration is very much an issue, he said. “The SOI we use is very thin so there’s a problem with creating the material (e.g., controlling film thickness),” explained Mayberry. Other challenges the company is addressing include making contact to the films and being able to land on the 22nm-thick silicon without punching through it.

Mayberry explained that Intel’s 3D modeling techniques for devices (e.g., exploring different conditions such as implant activation, gradients and doses, etc.) typically require calibration. The calibration is begun at one dimension and then the model is evaluated to see what it predicts for another dimension, followed by experiment and confirmation. J.M., D.V.


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