June 27, 2008 – Results presented earlier this year at SEMATECH’s EUV workshop in Bolton Landing, NY, indicate that photoresists used in EUV are proving to be twice as sensitive as previously believed, meaning they’re close to what’s needed for high-volume manufacturing. However, this also creates a further problem in that current EUV demo tools are only half as effective.
EUV photoresist sensitivity had been referenced to a 1990s-era Sandia Labs measurement technique, but in late 2007 workers at UC/Berkeley’s Lawrence Berkeley National Laboratory found that resist sensitivity was actually about twice that of the resist-based calibration standard. As a follow-up, NIST (prompted by Intel) says it independently validated the results at its SURF III Synchrotron Ultraviolet Radiation Facility. After developing a 300mm silicon wafer exposed with incrementally increasing doses of EUV in 15 areas, the seventh exposure was determined to be the minimum dose required (E0) to fully remove the resist (see Figure).
“These results are significant for a technology that faces many challenges before it is slated to become a high-volume manufacturing process in 2012,” said NIST researcher Steve Grantham, in a statement. “It should open the eyes of the industry to the need for accurate dose metrology and the use of traceable standards in their evaluations of source and lithography tool performance.”
The implications of these findings are significant. The good news is that the EUV resist is closer to high-volume manufacturability. The bad news: despite the 2x resist sensitivity to EUV light, NIST confirmed that exposure times were found to be the same — which means that only half as much light energy is arriving at the wafer as had been thought, so something in the EUV apparatus is performing at half the level it should. And NIST confirmed that scientists still don’t know what in the apparatus isn’t doing its job. Is it the mirrors (which by nature of EUV light only bounce ~70% of it to begin with)? Buffer gases? The power source itself? Other factors, or a combination thereof? All that’s known is that more research will be undertaken to figure out where the culprit is in EUV systems.
EUV has seen its window of opportunity for volume-grade semiconductor manufacturing slip from 32nm readiness to more likely 22nm, and Intel and IBM/AMD are thinking it’ll be after 22nm. The mixed message that some of the technologies being developed still require significant work to get right only creates more “haze” as to when EUV will actually be manufacturing-ready.
After developing a 300mm silicon wafer exposed with incrementally increasing doses of EUV in 15 areas, the seventh exposure was determined to be the minimum dose required (E0) to fully remove the resist. (Source: NIST)