by Ed Korczynski, Senior Technical Editor, Solid State Technology
June 13, 2008 – The next 10 years will witness more changes in mainstream IC manufacturing technology than in the last than in the last 40 years combined. Innovation will continue despite (or because of) limits in 2D scaling. With rapidly escalating costs projected for ≤32nm-node digital CMOS manufacturing, IC companies are turning to analog, packaging, and heterogeneous integration to add greater value for lower cost and risk. In short: unique process integration challenges at each fab will drive everything, as shown recently by presentations at the recent International Interconnect Technology Conference IITC.
What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be in the metrology space. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years (with the probable exception of EUV lithography). New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same.