Toshiba: Modeling technique boosts 45nm gate density

June 19, 2008 – Toshiba says it has developed a new compact model for circuit design that improves gate density for 45nm CMOS technology by 2.6× that of 65nm process technology, better than the 2.0&times expected with a node migration.

The new technique predicts performance of each transistor individually by focusing on factors dependent on circuit layout. In 65nm CMOS major factors include gate length and width, and the distance between the gate and isolation area (see Figure 1); at 45nm added considerations such as space of gates and location of contacts are modeled and included in the design (see Figure 2). By estimating each transistor characteristic and feeding them back into the circuit design, Toshiba says it can achieve higher gate density without increasing the margin for variability in design.

Before the 45nm node, advancing process technology migration involved shortening gate lengths and applying stress enhancement techniques, but beyond 45nm gate length scaling will increase significantly, and stress enhancement will produce complicated variability as a result of dependence on design layout, Toshiba notes in a statement. Earlier process technology generations avoid this by increasing design margins or restricting the pattern design, but this also crimps the ability to improve gate density and is thus not feasible for sub-45nm CMOS.


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