By Darren James, Rudolph Technologies, Inc.
With the cost of some advanced packages reaching several times the cost of the die they contain, the value contributed by functional testing, which allows manufacturers to avoid the cost of packaging defective die, has grown dramatically. Of course, testing has its own costs in both money and time. In addition to capital expenditures, ongoing maintenance, and consumables expenses for test equipment, testing adds as much as several hours per die to the manufacturing process, and several months to product development cycle. The increasing influence of functional testing on profitability has led to careful scrutiny of test processes in a continuing effort to optimize cost-benefit ratios. Probe card test and analysis, which provide the physical interface between the tester and the integrated circuit, has provided significant returns in areas ranging from the development of new probe technologies, to the management of probe card inventories and repair/refurbishing procedures.
Probe card test and analysis looks at several key attributes of probe configuration and performance, including probe planarity and alignment, contact resistance and leakage, and overtravel behavior. Probe manufacturers use this information in the development of new products and technologies, and to help assure the quality of probe cards shipped to customers. Device manufacturers can use the same information to qualify new or repaired cards, develop test procedures, predict scrub characteristics relative to probing requirements, manage card life cycles and inventories, and speed card repairs.
For example, with probe card prices increasing dramatically, reducing card inventory can provide significant cost savings. The rising prices for probe cards reflect the development of new technologies that increase test throughput by testing large numbers of die simultaneously. The most advanced cards, designed to test all die on a 300-mm wafer at the same time, can cost hundreds of thousands of dollars each. Probe cards are subject to wear, contamination, and damage during use. They must be inspected frequently and removed from service periodically for maintenance and repair. To minimize tester downtime and maintain process flow, manufacturers maintain an inventory of spare cards ready to be swapped into the process as needed. The ability of probe card analysis to improve the speed and reliability of inspection and repair processes delivers immediate cost savings by reducing inventory float requirements.
Traditional probe card testers use a multi-touch approach. Probe planarity and certain electrical characteristics are measured by lowering the card toward a flat, conductive test surface, and noting the height at which each probe makes contact. To measure alignment, small sets of probes are moved over an optical window and probe positions are measured at the nominal contact level and again with the specified overtravel. Each measurement covers only a fraction of the card and the sequence of measurements becomes very long for large cards. The accuracy of the measurements is dependent on the stage positioning and care must be taken to check for wear and debris accumulation on the optical window.
The same economic realities that have resulted in the development of full wafer probe cards have driven the development of probe card testers that can analyze an entire full-wafer card with a single touchdown. One company’s probe card test and analysis system* uses a proprietary three dimensional optical comparative metrology (3D-OCM) technique to provide one-touch measurement of the full probe card (Figure 1). The technique relies on a large, very flat, transparent measurement surface that includes a highly accurate fiducial grid. A scanning optical head looks through the grid at the probe tips, which are positioned close to but not in contact with the measurement surface, to derive 3D positions for the undeflected probes. The tips are then lowered to the overtravel position for a second measurement.
Conclusion
The semiconductor industry’s wafer test road map mandates faster and more accurate metrology technology to reduce the testing costs of today’s larger wafers and to help speed product time to market. One touch 3D-OCM measurements reduce probe wear and eliminate stage accuracy as a source of error; ultimately improving the speed, accuracy, precision and machine-to-machine correlation of the measurements. For both probe card manufacturers and device manufacturers, these benefits permit faster development of new products and processes, streamlined outgoing and incoming quality assurance and probe card qualification, and reduced costs for probe card maintenance and repair.
DARREN JAMES, Product Manager may be contacted at Rudolph Technologies, Inc.,
4900 West 78th Street, Bloomington, MN, 55435. Rudolph Technologies, Inc. Email: