AMAT: Double patterning gaining favor for 3X litho

by Katherine Derbyshire, Contributing Editor, Solid State Technology

July 24, 2008 – Every day last week during SEMICON West, there were lines out the door and up the block of the Apple store near San Francisco’s Moscone Center. People were waiting to buy the new 3G iPhones, in either variety (or both) with 8GB or 16GB flash memory.

These, and devices like them, are largely responsible for the re-emergence of memory as a driver for IC manufacturing. Logic circuits face severe challenges as transistors shrink, and the need for ultrashallow junctions and thinner gate dielectrics are driving radical changes in logic device manufacturing. (See related articles in SST‘s July 2008 issue: “32nm node USJ formation using rapid process optimization metrology, and “High-k goes to production, but arguments continue”.) Memory devices, though, face very few physics-based constraints; packing more data into a smaller area is almost entirely a function of the patterning and deposition methods used. Flash memory manufacturers were the first to adopt immersion lithography, and will probably be among the first to adopt EUV equipment once it’s available.

Yet memory firms also face a gap between the extendibility of immersion and the likely availability of EUV. According to Jan Smits, senior VP for ASML’s Twinscan business unit, 38nm half-pitch probably marks the limit for single exposure immersion lithography for flash devices. If EUV isn’t ready in that time frame, he expects double patterning will be needed to bridge the gap.

Double patterning is not necessarily a lithographic technique, though. While it’s certainly possible to expose and develop two layers of resist for a single etch step, suppliers of deposition and etch equipment argue that self-aligned spacer technology can achieve better results, at least for highly repetitive patterns like memories.

Ken MacWilliams of Applied Materials’ Maydan Technology Center, explained the company’s approach to self-aligned double patterning. It begins with two layers of an amorphous carbon mask material, with an oxide stop layer between them. The first and only exposure patterns the uppermost amorphous carbon layer with trenches, spaced at double the intended feature pitch; then a nitride spacer material coats the top and sides of these features. Etch steps clear the excess nitride from on top of the amorphous carbon layer, then remove the amorphous carbon layer itself, leaving behind two nitride spacers for each amorphous carbon line. Finally, another etch step transfers the resulting pattern to the second amorphous carbon layer, which serves as the process mask.

MacWilliams says the CD uniformity depends on the thickness uniformity of the nitride spacers — and process engineers have a good understanding of film thickness control. Moreover, the single exposure means that all lines will conform to the same statistical distribution. With double-exposure techniques, the final results depend on the sum of the two exposures; overlay and CD uniformity variations are additive. Applied Materials claims that it can achieve better overlay (<3nm) , uniformity (<3.5nm for spaces), and line-edge roughness (<2nm) for the 3Xnm memory node than are possible with lithographic techniques. MacWilliams said that self-aligned double patterning is emerging as the de facto standard for the 3X NAND generation and is beginning to be implemented in DRAMs.

Past history has shown that manufacturers will go to great lengths to avoid new exposure technologies. That is likely to be especially true when the new technology is as radical a change — and as fraught with uncertainty — as EUV continues to be. Though double patterning poses significant process challenges, it appears to be emerging as the safer choice. — K.D.


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