Economics, design issues top device-scaling concerns

by M. David Levenson, Editor-in-Chief, Microlithography World

July 23, 2008 – Device scaling is at the heart of Moore’s Law and progress in semiconductors, but technologists increasingly worry about the viability of the next steps. These issues were aired at a SEMICON West TechXpot discussion on Thursday (7/17).

Discussions began with Lars Liebmann of IBM musing about profitability at 32nm and beyond. There are no new lithographic exposure technologies in the offing, he warned, and the economics of computational lithography are different from that of exposure tool upgrades. Whereas the cost of a new scanner can be amortized over two or more entire generations of chips, the investment in computer simulation must be recovered with only a few chip designs. Thus, while computation is cheaper than new hardware, that does not mean that it is more economical for the industry, he said.

To profit in the new sub-sub-wavelength era, Liebmann recommended a systems approach to design that synergistically optimizes the few components that contributed provable value, and could be amortized over a broad range of products and a long time horizon. He cited OPC implemented fab-wide as a good example, and mentioned chip-specific design-for-manufacturing (DFM) as a counterexample.

Liebmann also warned against being seduced by “silver bullets” like double-patterning technology (DPT), which he noted would be needed at different nodes for different tasks. DPT was already in production for line ends at 45nm, he noted. [IBM and Infineon have published work using DPT to solve gate linewidth variations — see Microlithography World 17.2 , May 2008, p7.] Liebmann also reported that a Power PC chip had been implemented in a gridded design using PdBrix, without increased area but with better yield. Such “co-optimized prescriptive designs” were the way to continue device scaling profitably, in his view.

Milind Weling of Cadence reviewed the challenges of splitting a design for double patterning, especially when there were multiple options for the patterning technologies. Weling pointed out that the recent SEMATECH Litho Forum came to a consensus that DPT would be essential for the next two nodes or so (to 22nm and possibly beyond), so in his view some investment is warranted — but the challenge is that there are several proposed DPT paradigms requiring diverse models for implementation. Cadence has developed heuristics that provide a complete DP-compliant DFM flow (with verification, density balancing, and split minimization) for all types of DPT, he claimed.

From the design side, making money means doing the least possible computation-driven layout modification, pointed out Michael Buehler-Garcia of Mentor Graphics. He advocated implementing DFM processes across all steps of design, from rule development to tape-out.

Tracy Weed of Synopsys highlighted the importance of yield management for 32nm and beyond. Unpredictable yield was “the elephant in the room,” he worried, and advocated design-for-test, corrective methods, and cost control.

Nobuhito Toyama of DNP described the reticle industry’s struggles with DFM. The first wave (OPC) disturbed the maskmaking infrastructure, while the second wave created wafer-patterning hotspots that were undetectable on the photomask, he reported. Today, tools exist for intelligent fracturing of layouts and to deal with specific problems (like hotspots and slivers), but they have not yet been integrated into an effective system, and the technologies are still chasing the specifications, observed Toyama.

Mark Mason of Texas Instruments concluded by pointing out that device scaling is first and foremost an economics issue; if it doesn’t pay off, it will stop. He pointed to two issues as to why it might stop — potential barriers of fabrication costs and variability — but observed that both could be helped by some form of DFM. One problem is the diversity of DFM terminology and viewpoints, something that he is trying to solve as chairman of the DFM consortium within the SI2 Alliance, working toward common definitions and visions.

Audience members expressed deep skepticism during the Q&A session. Are the EDA partners of the chipmakers actually providing value, or should just they go home and let the IDMs write their own tools? How can you design so that DPT works in multiple foundries? Panel members seemed aware of the problems, but offered no pat solutions. — M.D.L.


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