by M. David Levenson, editor-in-chief, Microlithography World

July 14, 2008 – IMEC and ASML’s announcement that they have built functional 32nm SRAM cells (FinFETs) with 50nm contact holes exposed using EUV lithography.

Essentially what they’ve done is to print 45nm CD contact holes with a 50% exposure latitude using EUV. With DUV, exposure latitude would have been 6x-8x smaller and the most likely method would have been to print larger contacts and then shrink them with some resist-bloating method like RELACS. It’s likely that by “direct patterning” IMEC and ASML mean they don’t need such a step, or double patterning to hit the pitch needed. Oxide CDs are smaller than the resist CD, which suggests process control is key.

The SRAM design is not double-patterning friendly as Intel’s 32nm demo is (and Intel is closer to production), but the accomplishment is real. This may be an example of using processing expertise to overcome design limitations, whereas Intel has done the opposite. That is the basic tension in DFM, and the payoff.

32nm SRAM device after EUV ADT exposures with various doses and after oxide etch. (Source: IMEC)