BY DIONYSIOS MANESSIS and ANDREAS OSTMANN, FRAUNHOFER IZM
Following the path of electronics evolution, many technological concepts such as system-in-package (SiP), system-on-chip (SoC), and stacked chip packaging have drawn exploration roadmaps for higher system integration. Current technologies provide organic substrates with high-density build-up layers and micro-vias, equipped on both sides with surface mount passive components and active chips in packages. The lateral space shrink of active components on a board has been further achieved by using CSPs, flip chips, or stacked chips connected to an interposer substrate or lead frame by bond wires. Many novelties have led to a progressive evolution of the 2D-SiPs to a 3D build up, or 3D-SiP. Nevertheless, further miniaturization in 3D-SiPs is required and can be achieved by 3-D integration of components.
System requirements for signal frequencies in the order of several GHz can not be met by long bond wires and extensive interconnect paths on a board. To maintain signal integrity, much shorter and impedance-matched interconnects are required. Embedding technologies of passive and active components have come dynamically into play to lead the way towards highly miniaturized 3D-SiPs. A number of different embedding approaches have been presented in the past.1 Among the most recent technologies, the integrated module board (IMB) technology was developed by Helsinki University of Technology, in which chips are embedded in cavities into the core substrate.2 Industrialization plans for the IMB technology are being pursued.
 Figure 1. In CiP, electrical contacts are realized by laser-drilled and metallized micro-vias. |
Fraunhofer IZM, in collaboration with Technical University of Berlin has developed the chip-in-polymer technology (CiP) for embedding active chips for SiP applications. Significant developments of the technology have taken place in the framework of an EU-funded project, HIDING DIES, where active components were embedded by lamination of resin-coated-copper (RCCs) layers.3 The basic concept involves embedding thin chips into build-up layers using well-established PCB technology. Electrical contacts to the chips are realized by laser-drilled and metallized micro-vias (Figure 1). As part of the HIDING DIES Project, Fraunhofer IZM has further developed generic CiP technology to offer versatile solutions for the realization of 3D-SiP modules. Another embedding approach involves embedding a flip chip with very thin bumps into build-up layers.4
CiP Technology
Wafer preparation. Laser drilling of micro-vias and the PCB metallization process is not compatible with contact pads of semiconductor chips. Therefore, another layer of 5-µm Cu is applied to the bond pads of the chips being embedded. Wafers are thinned up to 50 µm. The present technology can handle contact pitches up to 150 µm by forming micro-vias directly to the chip pads. Prototype work has extended up to 100-µm peripheral pad pitch.
Chip placement and bonding. Placement accuracy is extremely crucial for chip embedding. Placement accuracy of