by Debra Vogler, Senior Technical Editor, Solid State Technology
July 14, 2008 – Kicking off SEMICON West, IMEC says it has been able to achieve electrically functional 32nm SRAM cells (FinFETs). The fin and gate levels were prepared using immersion lithography, but the contact hole level was exposed using EUV lithography (hole size 50nm). The work was done on ASML’s alpha tool installed at IMEC.
Although this work was done at 32nm (back in Feb. IBM and AMD announced a working 45nm test chip using EUV lithography for the first critical layer of metal interconnects), the ultimate target is for a production-worthy EUV tool at 22nm. In the PR announcing this latest EUV work, IMEC optimistically said it is “stimulated” by such milestones and “a concerted effort” from all EUV parties, and is “determined to advance EUV full-speed toward the 22nm node.”
“Memory companies will most likely insert EUV at 22nm to obtain the required half-pitch, while many logic manufacturers will be able to delay EUV insertion until the 16nm node, which for them corresponds to a 22nm half-pitch,” explained Kurt Ronse, program director, advanced lithography, at IMEC, in an interview with SST.
The consortia also is studying which layers can be exposed using EUV beyond the contact layer, and which would be exposed using immersion lithography. “We are looking at 3-4 layers or more using EUV at 22nm half-pitch,” Ronse said.
ASML’s roadmap still calls for a high-volume EUV tool to be ready by the end of 2009 or the beginning of 2010, according to Ron Kool, VP of ASML’s EUV business unit. “We expect a source will be ready in time, and overlay numbers between EUV layers and immersion layers will be ready as well,” he said. The most important task now, he noted, is achieving high throughput — which translates to getting a source that supports that capability.
Stimulated by these milestones and with a concerted effort from all actors involved in EUV research, IMEC is determined to advance EUV full speed towards the 22nm node. — D.V.
32nm SRAM device after EUV ADT exposures with various doses and after oxide etch. (Source: IMEC)