July 14, 2008 – European R&D consortium IMEC says it has come up with a method to produce ~50μm thin crystalline silicon wafers for use in solar cells, that uses available tools and is potentially kerf-loss free.

The process involves screenprinting a metallic layer on top of a thick crystalline Si wafer and annealing it in a belt furnace at a high temperature. When the wafer cools, the difference in metal/silicon thermal expansion coefficients induces a stress field in the substrate, which grows into a crack close to and parallel with the wafer surface. The top layer of Si and attached metal layer snap off, and the metal layer is etched away from the silicon foil, leaving a “clean and stress-free ultrathin silicon foil — and the remaining substrate can be reused to peel off further layers.

Thermo-mechanical model of the lift-off process. (Source: IMEC)

IMEC says it has demonstrated the process on single- and multi-crystalline silicon as well as on Cz (Czochralski) material with different orientations, producing foils with 25cm² area and 30μm-50μm thickness. One of these foils was further processed into a 1cmsolar cell using a heterojunction emitter process, and it reached 10.0% efficiency without backsurface passivation or intentional surface texturing, suggesting the material quality “is largely preserved during the lift-off process in spite of the large stresses involved,” IMEC said in a statement, adding that it should be able to use both passivation and texturing “to reach much higher efficiencies.”

Ultra-thin crystalline Si foil; this side shows the surface cut from the thicker substrate. (Source: IMEC)