by Griff Resor, Resor Associates, SST editorial advisory board
There were no surprises at Wednesday’s Sokudo litho breakfast, which was good news. Glen Mori of Sokudo did a nice job of organizing a review of double patterning methods, including Applied’s spacer method. The content was very similar to what one could have heard at SPIE in February, but it was helpful to hear it again, all in one place and all at one time. The focus was on the 32nm node.
Harry Levinson of AMD began with a quick overview of the methods one can choose from. Mark Slezak of JSR presented their work on litho-freeze-litho-etch (LFLE), in which the advantage is the wafers stay in the litho cell and don’t change shape due to an etch step between the two litho steps. The “freeze” step (a chemical process, not a thermal one) uses a spin on overcoat to cross-link the first mask’s pattern.
Mori discussed how his company must support all these methods of double patterning, so it is working with everyone to define basic process modules for their track systems. Chris Ngai presented Applied Materials’ spacer technology, which is now in production for flash memories. Chris Ngai from Applied Materials showed 22nm spacer results. Robert Socha of ASML followed with how the various methods impact the scanner requirements. Spacers are not popular with many of ASML’s customers, so the machines must be improved to support double exposure and LFLE methods. This involves significant reduction of overlay errors and CD errors.
Finally, Chris Sparkes of Nikon discussed what his company is doing to meet the needs of various double patterning needs. He presented cost-of-ownership (CoO) calculations showing that the spacer method is the most expensive, due to the many deposition and etch tools required. Also, extra masks are needed to trim off unwanted spacer material and to fill areas that the spacer method does not fill.
From these talks, three things seem clear:
– Scanners are improving rapidly enough to meet the 32nm node’s need for double patterning;
– LFLE may be the lowest-cost method (and it seems to work); and
– Chip sets with many prints/mask will be cost-effective, but short mask life (2000 prints/mask) will be much more expensive.
In summary, some form of double patterning will be used with optical scanners for the 32nm node. — G.R.