By Paul Lindner, EV Group, St. Florian, Austria
Well-established as a process for forming silicon-on-insulator (SOI) substrates, wafer bonding is increasingly broadening its horizons to encompass bonding wafers for a variety of fast growing applications. Regardless of the materials involved, packaging has emerged as the primary underlying driver. As wafer bonding technology evolves to overcome customer challenges and the limitations of existing solutions, key market, technology/application, and industry trends can all be linked —directly or indirectly — to emerging advanced packaging requirements.
MEMS
Microelectromechanical systems (MEMS) are an early and ongoing application for wafer bonding. Being a wafer-scale process, wafer bonding brings some major advantages for these applications such as improved throughput, the possibility to shrink the form factor as well as the thickness of the devices, the ability to encapsulate the device under special atmospheric conditions and finally and most important, to reduce package cost . Before the use of wafer bonding/WLP, for some applications, MEMS packaging represented as much as 70% of the total device cost. This has been successfully reduced to as little 20-30 % (not counting the cost for testing), thanks to a strong focus on total cost of ownership (TCO) early in the design of bonding equipment.
MEMS sensor devices are being used in a growing number of applications, which in turn bring technical challenges. Some special applications require wafer-level packaging with hermetic cavities under vacuum, creating the need for wafer bonding equipment that can be used in high- or ultra-high-vacuum environments. These include:
A wafer bonding technique developed to accommodate these requirements uses getter materials to ensure suitable vacuum (total pressure <1x10-3 mbar) and long-term stability in MEMS devices. Gettering is essential for selective pumping of gases into and contaminants out of the MEMS package to create strong seal.
Consumer electronics such as cell phones are one application driving future sensor developments, as sensors will increasingly act in a way that improves the functionality and usability of the device.
Total Cost of Ownership
The quality of the technology alone is not enough to spur customers to adopt a new process or system. With customers more cost-sensitive than ever before, equipment must be designed with TCO issues in mind — critical factors as yield, process time, investment cost, uptime, throughput and upgrades.
What this means is that customers’ concerns must become suppliers’ concerns, with a focus on building close, cooperative customer relationships that take these TCO factors into account. As suppliers become more involved in the whole process chain, customers are more inclined to want a total solution, which can complicate matters. However, when customers find a solution that works, is reliable, and helps yield, they’re not likely to change just because a hot new one comes along. The cost of switching is very high, and it takes a lot of time to convert to a stable new process with higher yield. Thus products must support future device generations — the proven technology must be scaleable — by forward-looking equipment design or through field upgrades.
Wafer preparation and device design are the two most important criteria for a stable process. When customers have confidence in a supplier with proven capability in these areas, they are more inclined to adopt new technologies.
Packaged Silicon Wafers
In its initial incarnation, wafer bonding in the packaging of silicon structures was used for MEMS. Its main purpose was wafer-level capping of fragile structures, ensuring the structures were sealed away from the surrounding environment.
Today, wafer bonding is being used for 3D interconnect in addition to capping, shifting its application forward in the manufacturing process. Through-silicon vias (TSVs) are being used to connect MEMS, CMOS image sensors (CISs) and memory devices. The newest requirement for wafer bonding is that companies creating 3D integrated bonding schemes work in the front-end of the process line because these companies are largely coming from the CMOS world, not the MEMS world. Moving wafer bonding into the FEOL will have a major impact on the front-end, creating more requirements for addressing CMOS compatible cleanliness, etc.
3D Interconnect
Using 3D integration technology/TSVs delivers a 30-40% compound annual growth rate (CAGR) to users, on a worldwide basis. The two emerging applications today are CISs packaging with backside illumination, and DRAM stacking, which utilize polymer (adhesive) bonding or direct oxide bonding. For next-generation 3D, CMOS integration metallic bonding techniques are currently in the lead — such as Cu diffusion bonding.
Not only are new types of packages being explored, silicon integration also continues to gain ground through implementation of system-in-package (SiPs) and 3D stacked solutions (both die and packages). TSVs offer notable cost and performance advantages, and initial products incorporating TSVs are expected to reach the market in the second half of this year, with the first users being memory and specialty product makers followed shortly thereafter by logic providers. Thinner wafers will be used, enabling creation of shorter, smaller-diameter vias with lower aspect ratios to bring costs down even further.
Paul Lindner, executive technology director, may be emailed at [email protected] For more information visit www.evgroup.com