VLSI Symposium: Panelists, interviews about the need (or not) for SOI

by John O. Borland, Editorial Advisor, Solid State Technology

It was 10 years ago that SOI “finally arrived,” as VLSI Symposium attendees were reminded by the Tuesday evening panel discussion — two participants of which, Ghavam Shahidi of IBM and Mark Bohr of Intel, were also on the first SOI panel discussion in 1999. Others on this year’s panel included Eiichi Suzuki of AIST, Atsushi Kameyama of Toshiba, Reinhard Mahnkopf of Infineon, Carlos Mazure of Soitec, David Scott of TSMC, and Masami Usami of Hitachi.

Nine years ago the industry was on 200mm wafers, using 180nm process technologies and a SiO2/poly gate stack. Today, in 2008, we are on 300mm wafers at the 45nm node, with high-k and metal gates (HK+MG), bulk CMOS still dominates, and the ITRS says planar CMOS ends at 2012. For now SOI and bulk camps remain as they are, but SOI will be relied upon beyond the 22nm node. Mahnkopf said SOI has advantages over bulk, but bulk will be mainstream for the next 10 years. Mazure noted that 10% of 300mm wafers consumed for digital logic are SOI. At the next wafer size (450mm), SOI will be cost-effective because of STI process complexity, Mazure added. TSMC’s Scott said bulk CMOS dominates and that TSMC has fully demonstrated 65nm and 45nm node SOI devices, but no customers want it — “They built it (SOI) and customers did not come!” A 10%-20% performance benefit with SOI is not enough, and it needs to be >50%. Suzuki said the key for sub-22nm is FinFET, which means SOI and not bulk (he added that there is much research in double gate/FinFET). In the next 10 years, SOI will be mainstream, he claimed, adding that MEMS and bio integration also will be important.

Bohr also showed a benefits and cost comparison:

Benefit Cost








15% performance,
>10× leakage


Mainstream will be bulk+strain-Si+HK/MG which is still better than PD-SOI+strain-Si, Bohr said. He added that floating body cell (FBC) — which Intel discussed separately at the VLSI Symposium, in paper 9.4 — may justify SOI, but at the 16nm node, they will need double gate (FinFET), which can be on either bulk or SOI wafers. Kameyama said that today, SOI is in mass production and also bulk MP with HK+MG, so the main issue is on the business side and initial investments costs with SOI, so bulk will still be the mainstream for the next 10 years. Usami focused on RFID devices and said SOI is best.

During the open panel discussion, Mazure said the SOI wafer cost by 2010 will only be $400 more than bulk — vs. 3× more than the best 300mm bulk or epi wafer today. Shahidi said FinFET in SOI is the best because bulk FinFET requires heavy doping which leads to leakage degradation. At the end of the panel session, participants took a vote and the majority believed bulk will still dominate over the next 10 years.

IMEC: FinFET at 22nm, bulk and SOI

During an exclusive private breakfast meeting with SST, IMEC’s Luc Van den hove, executive VP & COO, and Thomas Hoffmann, device manager, discussed the consortium’s work discussed at this year’s VLSI Symposium, which included seven technology papers and a paper on circuits. For the 32nm node, they reported using a Hf-oxide base layer and adding capping layers for their dual high-k single-metal gate structure reducing the process complexity by 40% for low cost. For pMOS they use HfSiON/Al2O3 and for nMOS HfSiON/La2O3 or Dy2O3 and a k value about 11.

For the 32nm node, IMEC is studying planar CMOS with major programs focused on gate stack engineering, strain-Si with eSiGe for pMOS, and eSiC for nMOS, and laser annealing for USJ. For eSiC, their process of record is by SEG, but they are also looking at carbon implantation as an alternative to determine the best cost-effective technique. They also say stress memorization technique (SMT) still works with a HK+MG gate-first process flow. With laser annealing, IMEC sees advantages with HK+MG improving the interaction with the capping layer. At the 22nm node, they see FinFET as a viable option, and they are studying both SOI and bulk FinFET because most of their members are memory companies requiring cost-effective solutions. (The full list of IMEC’s sub-32nm CMOS partners includes: Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, TI and ST.) Among the major challenges is how to dope the FIN; and metrology is also a key issue for FinFET with 3D doping, they said. Other challenges include optimizing the etching process and what technique to use for process boosters such as strain-Si.

IBM: “First” SOI adopter looks ahead

Gary Patton, VP of the semiconductor research and development center at IBM, and Mukesh Khare, manager of HK+MG technology, both sat down in exclusive interviews with SST after the Wednesday (June 18) sessions. They listed what leading-edge technologies IBM offers to their customers in both SOI and bulk CMOS technology in three areas: 1) low-power bulk technology, 2) general-purpose bulk technology, and 3) high-performance MPU with SOI. (This a change in IBM’s public message, which had been “all our devices are SOI,” to “we will also do bulk CMOS for our partners.) For the 45nm node, the key was high-density eDRAM and with an SOI wafer, the trench capacitor oxide collar was replaced with the buried oxide. They reported on a 32nm-node HK+MG device, targeting 32nm low-power for their bulk wafer customers at low cost. Their process uses immersion lithography and a work function layer/cap, resulting in a less-expensive process and 30% overall improvement. They also pointed out that their HK+MG process reduces Vt mismatch compared to SiON/poly by 40%. Moreover, they said that at 32nm, it is a wash between SOI and bulk CMOS in terms of wafer cost, process complexity, chip size, and package costs and power.

Intel: SOI-only for 16nm? Maybe not

In a final private meeting at the VLSI Symposium, on the final day (Thursday 6/19), Intel senior fellow Mark Bohr reviewed the key points from his SOI panel discussion: Intel cannot justify the cost benefits of SOI. While the 16nm node will require double gate (FinFET), he pointed out that one does not need SOI FinFET; bulk FinFET results look very good, as was shown during the event’s short course. He did note, though, that FBC may justify SOI as described in another Intel paper.

Discussing other papers presented at this year’s Symposium, Bohr noted that similar to results disclosed by Sony, Intel also saw that the replacement gate process enhances the eSiGe compressive stress in the channel, and this boost in pMOS performance makes the pMOS device almost as good as the nMOS (only 21% difference now). J.O.B.

John Borland is founder of J.O.B. Technologies, and a member of SST’s Editorial Advisory Board.


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