Packaging, Novel Interconnect Methods Examined at SMTAI

By Meredith Courtemanche, managing editor, SMT
I was afraid Florida would be too hot to visit in August for SMTA International (SMTAI) 2008. The sun was no concern, as Hurricane Fay winds tossed about the palm trees outside the convention center. Safe inside, we concentrated on the next big thing to hit the electronics interconnect community: thru-silicon via (TSV) and other chip/package/board manufacturing technologies.

“3D Stacked Packages: Which Way to Go?,” which I co-chaired with Gail Flower, editor-in-chief,SMT and Advanced Packaging; brought academic Ritwik Chatterjee, Ph.D.; industry consortium representative Rozalia Beica; materials scientist Scott Kennedy; OSAT provider Lee Smith, and trends-tracker Jan Vardaman together. What is package integration? Where are the barriers to new technologies? What markets could benefit? And how can we attain these integration goals, from silicon to PCB?

Ritwik Chatterjee, Ph.D., speaking on behalf of the Georgia Tech Packaging Research Center (PRC), defines 1st and 2nd level interconnect integration as a combination of all-silicon monolithic packaging and embedded technologies that bring passives and actives into the module substrates themselves. All-silicon interconnect combines the semiconductor manufacturing steps of front-end-of-line (FEOL), back-end-of-line (BEOL), and packaging into a single flow. Lee Smith, VP of business development at outsourcing semiconductor assembly and test (OSAT) provider Amkor Technology, was instrumental in developing the package-on-package (PoP) stack that has become such a cost-, time- and yield-effective process that many EMS providers now stack BGAs in the standard pick-and-place step of board assembly. Rozalia Beica, senior process engineer at Semitool Inc. and representing the EMC3D consortium, expressed integration in terms of making standard-form-factor ICs more 3D with greater TSV adoption. Kennedy, senior development engineer at Rogers Corporation, looking at the potential inherent in package substrates, advocates a move away from ceramics to more PCB-like materials that can compensate for coefficient of thermal expansion (CTE) mismatch and signal loss in new packages better than conventional materials.

Plenty of roadblocks stand in the way of these new technologies. As Smith says, sometimes trying to use just one integration technique

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.