SEMICON Europa’s Advanced Packaging Conference Shifts Focus from TSV to WLP

By Françoise von Trapp, managing editor

STUTTGART, GERMANY — Shifting away from focus on 3D IC and TSV processes, this year’s Advanced Packaging Conference, at SEMICON Europa, titled “Technologies, Manufacturing And Supply Chain”, will focus on more immediate issues facing the back-end sector of the semiconductor industries. The conference takes place on October 9 and 10, 2001 in Stuttgart, Germany as part of the SEMICON Europa program. Eef Bagerman, general manager operations, back-end innovation, NXP Semiconductors offered some insight about how the program was selected, and what technologies will be most likely to spark discussion.

Moving away from a program devoted to TSV processes was a conscious decision of the committee, Bagerman said. They didn’t want to repeat last year’s topic, and there is a lot to talk about with wafer-level and multi-die packaging processes that addresses current production capabilities. “With TSV, we are still struggling to find application areas,” he said. Other than image sensors which are an obvious fit, he said it’s still not determined to be the best solution for multi-die packaging.

While there has been a great deal of activity focused on miniaturization and system integration in the past year, cost is still the limiting factor. As die cost is decreasing due to the transition to 300-mm wafers, assembly costs continue to rise, he explained. “The package is still the connection to the outside world,” he noted, adding that the gap is expanding between package and die cost, and there is more pressure to come up with breakthroughs to level the trends.

According to Bagerman, an interesting trend is the adoption of flip chip over traditional wire bond as gold prices have more than doubled in the past two years. There has also been a wider acceptance of wafer level packaging. One technology issue that needs to be addressed is the size of the die in relation to the bumps that have to be put on it. Bagerman says one solution is moving away from an interposer to a fan-out package, which gives the die more space to get things done.

One topic of discussion Bagerman expects to see at SEMICON Europa will be the debate between embedded die and fan-out packages. He says with embedded die, the infrastructure and value chain must be considered. Although its proven to work for discrete devices, with 99% substrate yields , its more difficult to reach those yields with expensive die with high pin counts. Known good die are required, and so far only 97% yield has been achieved, which removes the cost benefit. Bagerman says he is a proponent of the fan-out package, partly because NXP is an IC supplier, and partly because he sees it as a more viable option.

Developed in collaboration with IMAPS, and co-sponsored by Advanced Packaging magazine, the two-day conference will be divided into two sessions: “Advanced Manufacturing, Processes & Materials” and “Embedded Die & Wafer Level Packaging”; and will feature an executive round table, “Wafer Level Packaging & Embedded Die Supply Chain – Who Will Do It?” moderated by Françoise von Trapp, managing editor, Advanced Packaging and Solid State Technology magazines. Among the speakers, Jean-Christophe Eloy, of Yole Dèvellopment, will update attendees on 3D wafer-level market trends, and Eric Beyne, of IMEC, will discuss the research institutes’ alternative of high-density 3D stacking without TSV using ultra-thin chip embedding processes instead.

SEMICON Europa takes place October 7-9, 2008 in Stuttgart, Germany, and in addition to the test, assembly and packaging track, will feature business and technical programs in parallel to the exhibition in three additional tracks including Semiconductor; MEMS/MST; and Photovoltaic.


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