by Keith Cooper, business development manager, MEMS and LED, Suss MicroTec
Microelectrical-mechanical systems (MEMS) devices have experienced impressive and steady growth as they are integrated into people’s everyday lives. Since their conceptualization in the 1970’s, they have progressed from laboratory curiosity to integration in high-end systems, and, more recently, to widespread application in popular consumer devices.
With any market, certain forces will determine the direction and magnitude of any changes in the supply chain. These influences might include a user’s desires for greater functionality, a reduction in the cost to meet these desires, a reduction in the size or weight of the device, or even a radical innovation that interrupts current thoughts or methods. A number of factors have fueled this growth in demand for MEMS devices, ranging from gains in performance and functionality to new processes to lower the manufacturing cost for the devices, to fundamental changes in the technology and materials used in the device manufacturing.
 Figure 1: Permeability of materials.1 |
As the demand and product offering grows, a segmentation process often takes place whereby products are separated into categories marked by price and performance. This process may be quite intentional on the part of the suppliers, which seek to create and conquer segments where they can thrive. It also may be simply a natural flow of the market as evolutionary forces shape the direction and desires of the end consumers.
Since MEMS contain by definition some sort of mechanical function, they present special challenges to fabrication and packaging technologies. While fabrication technologies have largely kept pace with market demand, the enormous difficulties in packaging such devices have weighed down its progress, resulting in an inappropriate proportion of costs—for some devices up to 80%—being relegated to the packaging area. Wafer-level bonding for MEMS for first level packaging combined with through-silicon vias is widely regarded to be the next enabling technology for the entire semiconductor industry. The first step is the adoption of metal bonding methods compatible with first-level packaging and front- and backend fabrication.
As any MEMS device progresses from lab to fab, there must be a coordinated effort between the scientists, device engineers, process and assembly technologists, and the business group to carefully mark a path to pursue, taking into account market requirements, device performance, and material and process capabilities in deciding what the final MEMS architecture will be. If the goal is widespread use of a commodity part, the product’s life cycle will likely be marked by evolutionary revisions of the materials and production methods, to ultimately lower production costs and compensate for shrinking profit margins. If, however, the goal is to capture a higher-performance segment of the market with higher profit margins, the product’s life cycle will contain incremental gains in performance that have been enabled by progress in the technology, materials, and methodology to build the device. In either approach, the choices must be deliberate and thorough, and the equipment must be capable of delivering consistent results over the entire progress of the device.
In the MEMS world, several substrate-bonding techniques have been successfully applied in production. Each method has its advantages and disadvantages, owing to the material and processing costs, tolerance of manufacturing process variations process, and final device performance. The first two techniques to find wide acceptance were anodic bonding and glass frit bonding. The first used an electric potential between a pyrex and a silicon substrate to enable an electric field assisted diffusion bond and requires no intermediate layer, while the second requires the deposition of a frit material onto one substrate prior to alignment and bonding.
Though either technique could be used for a relatively low-cost bond, glass frit proved to be more tolerant of surface variations, since the screen-printed frit material would fill in any voids or gaps between the two substrates being bonded and reflow during the thermal steps to self-planarize the interface. Unfortunately, as the frit material densified during the bond process, its shrinkage led to non-uniform bondline thicknesses which could cause variations in device performance. Also, because the deposited frit material required real estate on the wafer, its use hampered device scaling which would help to lower manufacturing costs. A wider bondline to provide better protection from the environment and higher device performance was simply incompatible with device economics. Moreover, the viscous nature of the frit material during high-temperature bonding could lead to misalignments and non-uniform bondline thicknesses that would limit the design of smaller dice.
Another popular bonding method is fusion bonding, also called direct bonding. Like anodic bonding, it requires no intermediate layer between the two substrates—but unlike anodic methods, it can used with a wide range of substrate material types. Because fusion bonding depends on intimate contact between bond surfaces on an atomic scale, the requirements for surface finish are rigorous. Pursued initially for unpatterned Si wafers to make silicon-on-insulator (SOI) substrates, fusion bonding requires a surface roughness of about 0.5nm. After the initial bonding at room temperature, the bond must be annealed at temperatures at or above 1000°C, though this annealing temperature can be lowered substantially by plasma pre-treatment of the surfaces. Direct bonding has shown extremely strong bonds on Si-Si, Si-GaAs, Si-Ge, and many other materials combinations, but the surface requirements can be very challenging to achieve on processed surfaces. And since there is no intermediate layer to compensate between substrates, even very small particles between substrates will lead to large voids in the bond.
A more recent bonding methodology is to use metal alloys as the bonding medium. Since their deposition characteristics are well characterized as back-end bumping and assembly processes, the thickness and uniformity of the metal deposition process is well understood. Adoption of these materials in wafer-level packaging lay the groundwork for multilayer chip stacking and integrated packing scenarios with through-silicon vias. Eutectic reactions are a triple point in the phase diagram where solid alloys mixtures transform directly to a liquid phase. This mimics the reflow processes that are so desirable in glass frit sealing. Upon cooling, a very special microstructure evolves which is both strong and hermetic. Eutectic metal compositions have several benefits as sealing materials, including the ability to accurately deposit and define the metals in desired patterns, the tolerance to surface deviations, roughness and particulates, plus metals’ inherent hermeticity and conductivity.
Hermeticity, the degree of air tightness for a vessel or package, is especially important for MEMS packages because the mechanical and electrical functionality of the device within the package relies on critical environmental control. Any change in the atmosphere inside the package can bring about a shift in performance or even a total failure of the device.
Many technologists have thought of hermeticity as a binary measure—a package is either hermetic or it’s not. The reality is that hermeticity is a continuum, even though many have accepted an arbitrary line drawn at a permeability of about 10–14 gm/cm-s-Torr. Hermeticity determines the lifetime for a MEMS device, due to the interference of the permeating gas with the device’s functionality. For some MEMS devices, water vapor may be the invading culprit that corrodes the moving parts; for other MEMS devices, any gas which permeates the package will spoil the inert or vacuum environment necessary for any device function. One of the most areas most vulnerable to leakage is the bond layer which seals the MEMS device to its corresponding substrate.
In Figure 1, various materials are plotted permeability as a function of the seal surface width. Though no material is 100% hermetic, dense materials such as metals provide much greater protection against any gas intrusion and therefore provide much greater device performance and lifetimes. Since metals are much more difficult to permeate, a thin metal bondline will provide good protection against leakage, sometimes orders-of-magnitude better than glass frit materials of greater thickness and width.
Metal materials for bonding layers include elements such as gold, copper, or aluminum which, when joined with high temperature and high force, form a diffusion bond. To lower the process temperatures, eutectic alloys such as Au-Sn or Au-In have been pursued and characterized. These alloys melt at reasonable temperatures (these two examples at 282°C and 156°C, respectively), making the bonding process easier, faster, and ultimately lower-cost.
In order to fully realize the advantages of thinner metal bondlines, the alignment of the two substrates prior to the bonding step must be very precise; generally the alignment must be ~10% of the metal width (75%–80% overlap of upper and lower seals).
 Figur 2: Various alignment methodologies for substrate bonding |
An enhanced bonding system offers the necessary performance to utilize all the advantages of eutectic metal bonding. In the tool scheme, the two substrates are aligned using a configurable microscope system which images the substrates’ fiducial marks by visible or IR illumination front- and backside alignment of the patterns even buried within the substrates (as depicted in Figure 2). Auto-alignment software has been successfully employed to align various target designs and material types in a production scenario, delivering micron or sub-micron alignments.
 Figure 3: Typical alignment fixture to transfer aligned substrate pair. |
After alignment in the bond aligner, the two substrates are held by a fixture (Figure 3), then transferred to a chamber where the two substrates are bonded using a combination of force, temperature, and a variety of ambient conditions. Since the bonding process may include significant force and temperature—up to 600°C and many kN of force—this bonding fixture must precisely maintain the accurate alignment of the substrates under extreme conditions. The design of these bonding fixtures has been optimized over several tool generations, and they have demonstrated sub-micron performance in numerous bond processes.
Once inside the bonding chamber, a force column is used to bring the wafers together at a programmable force and temperature profile; each parameter can be ramped to meet specific material and process requirements. Before the force column (Figure 4) begins to press the wafer stack together, it is first allowed to level itself to the stack to minimize any alignment shift caused by any deviation from the normal direction. This leveling function, coupled with a rigid design of the force column, ensures that alignment errors are not induced while compressing the bondline. This is a very a critical task considering the viscous nature of the softened metal alloy. For temperature uniformity, a sintered SiN heater coupled with SiC pressure plates provide rapid and uniform heating and cooling of the substrates, and the CTE of the pressure plates closely matches that of commonly bonded substrates. Excellent temperature and force uniformity ensure consistent bonding over the entire wafer surface.
 Figure 4: Self-leveling force column for bonder. |
If a metal sealing ring were to be integrated into an existing MEMS device replacing a glass frit or polymer sealing technology, this one change in device layout would drastically increase the number of dice/wafer. Consider the example of a 3×3mm die currently using a 100µm wide bondline made of glass frit or polymer. Replacing that 100µm feature with a 10µm wide bondline made of a eutectic metal alloy would produce a device with equal or better hermeticity, with 351 additional dice/wafer (Figure 5). With this new physical layout, not only would the device performance be enhanced, but the economics of producing the device would be much more favorable. This change alone could easily shift a device line’s profit margins from an unattractive to a very attractive regime, without changing any of the device’s active regions.
 Figure 5: Changing a 100µm glass frit seal to a 10µm metal seal would allow for an extra 351 die for 9mm2 die. |
This scenario applies directly to several MEMS devices types, particularly inertial sensors and gyroscopes. After their initial use in expensive, specialized systems such as early automotive airbag systems, they underwent a maturation and miniaturization process whereby costs were greatly reduced to expand the available market. More recently, they have been enhanced by some of the technologies described here to improve the device performance while reducing overall costs. Applications for these devices have now been expanded from airbag sensors to include vehicle stability control systems, image stabilization for cameras, and many types of low-end and high-end gaming systems.
As markets develop and mature, a natural segmentation of devices takes place, characterized by a price/performance curve. Lower performance devices will always experience price pressures and methodologies must be refined to maintain a market position without ceding market share to lower-cost suppliers. Higher functioning devices, enabled by such technological enhancements as eutectic metal bonding with best-in-class equipment, will serve the high-performance needs of the market, providing higher selling prices at sustainable margins.
1 Stroehle, D, “On the Penetration of Gases and Water Vapour into Packages with Cavities and on Maximum Allowable Leak Rates,” Reliability PhysicsSymposium, April 1977, pp. 101-106; ISSN: 0735-0791.
Keith Cooper is business development manager for the MEMS and LED market segments at SUSS MicroTec. Prior to joining SUSS in 1985, Keith worked as a process development engineer for both Texas Instruments and Mostek (now ST Microelectronics) in Dallas, TX. E-mail: [email protected].