by Katherine Derbyshire, Contributing Editor, Solid State Technology
Oct. 20, 2008 – Though EUV lithography is creeping toward production readiness, it isn’t there yet. Several significant hurdles remain; manufacturers are unlikely to commit to EUV production until a production-worthy exposure tool actually exists. In the meantime, they still need to increase circuit density in order to remain competitive. NAND flash suppliers in particular face resolution targets as much as three years more aggressive than logic and DRAM manufacturers. These companies increasingly see double patterning as a bridge, spanning the gap between current single exposure 193nm immersion lithography and the emergence of EUV. Even once EUV reaches manufacturing, cost and low throughput may limit its use to only the most critical layers.
Several double patterning schemes exist, as ASML Fellow Jo Finders described at ASML’s recent Eindhoven (Netherlands) press event. The easiest to explain, a litho-etch, litho-etch (LELE) scheme, transfers first one mask, then a second to a hard mask layer, then uses the hard mask to pattern the underlying substrate. The LELE approach places extreme demands on both the productivity and the performance of the lithography tool. ASML’s new Twinscan NXT platform strives to address these challenges.
Because double patterning splits the mask pattern into two separate components, it relaxes the resolution requirements for each component. The half-pitch of each component mask can be double the half-pitch of the overall design. If the k1 factor from Rayleigh’s equation is seen as a difficulty factor (designs with k1 <1.0 require the use of resolution enhancement techniques; those with k1 <0.25 are generally seen as unmanufacturable), double patterning increases k1 and makes it possible to print designs that could not be rendered with a single mask. Yet the relaxation of CD requirements is achieved at the expense of a dramatic tightening of overlay specifications. In the simplest example, the second mask might place lines in the spaces left by the first mask (see Figure 1). An overlay error in mask B shifts the placement of the second group of lines, changing the width of the interlinear spaces. In a double patterning scheme, overlay error manifests itself as pitch error. As a result, double patterning imposes a maximum overlay error of just 7% of CD, compared with 20% of CD in an equivalent single exposure pattern.
Figure 1: Double patterning splits the design into two less demanding masks. (Source: ASML)
In conventional stage designs, stage placement is measured relative to the sides of the stage platform using laser interferometry. As the stage moves, however, it creates turbulence in the surrounding air. At the extreme overlay specifications required for 22nm double patterning, and the high stage accelerations needed to meet the required throughput, this turbulence can degrade the accuracy of the interferometry measurement. Instead, the NXT platform uses vertical interferometers to measure placement of the stage relative to an overhead grid plate (see Figure 2). The resulting light path is much shorter, reducing the impact of air turbulence.
Other changes in the new design focus on improved productivity. Because double patterning uses two masks for each circuit level, it potentially doubles the cost of these levels. Neal Callan, of ASML’s Brion Technology subsidiary, estimates that the 22nm node could require 10 or more double patterning levels, a substantial cost impact, particularly for the cost-sensitive NAND flash suppliers currently driving feature size reduction.
Figure 2: Measuring stage placement relative to an overhead grid reduces the amount of intervening air, limiting errors due to air turbulence. (Source: ASML)
While stage movement during exposure is limited by the resist sensitivity and laser intensity and pulse rate, the time needed to swap wafers and move the stage into position is limited by stage acceleration. In ASML’s Twinscan systems, one stage measures and aligns the wafer while a second conducts the exposure. In previous designs, swapping the exposure and alignment wafers consumed significant time. Limited by guide rails, the second stage had to wait for the first to get out of the way.
In the NXT platform, in contrast, the stages are autonomous, magnetically levitated platforms. When the alignment stage replaces the exposure stage, the two move as a unit, allowing the bubble of immersion fluid to move unimpeded from one to the other. The stages ride on a frictionless cushion of air, reducing the resistance to acceleration or deceleration. Further, the stage itself weighs 66% less than previous designs. According to Harry van der Schoot, wafer stage project leader for the NXT platform, this reduction was achieved without loss of stiffness by incorporating carbon fiber and other advanced materials in place of metals, and by making the stage more compact. Overall, the new platform delivers an initial 30% throughput improvement, much of it achieved by reducing the stage swap time. Further optimization is possible.
Figure 3: Reducing the overhead required to exchange stages substantially reduces the total exposure time per wafer. (Source: ASML)
At this time, double patterning using 193nm immersion systems is the most likely technology for the 32nm node, and is likely to be used by early adopters at the 22nm node as well. ASML and its customers hope that the new platform will ease the productivity and performance pain that such an extreme extension of optical lithography might otherwise impose. — K.D.