by Gail Flower, Editor-in-Chief, Advanced Packaging
IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip-chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages , an area of predicted high-growth, IMEC has announced notable achievements.
This October, IMEC engineers demonstrated the first functional 3D integrated circuits made by die-to-die stacking using 5μm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13μm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25μm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.
Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results will be presented at the IEEE-IEDM conference in San Francisco this December.
3D stacked IC with die-to-die stacking using copper through silicon vias (TSVs).
With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, program director of IMEC’s Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies, including equipment and materials suppliers Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Others include SATS provider Amkor; foundry SMC; ICOS Vision Systems for EDA work; fabless company Qualcomm; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.
Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after the FEOL, but before the actual BEOL. It takes advantage of the high-aspect-ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.
“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.
IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration — fab, packaging, or board-level assembly. The different 3D interconnect types include 3D-SIP, which uses traditional packaging interconnect technologies with wire-bonded stacked die, stacked packages or 3D interconnects at the 2nd and 3rd Jisso packaging identified levels. Another flavor is called 3D-WLP for 3D interconnects made post IC passivation or those at the 1st Jisso level. Finally, 3D-IC and 3D-SIC could happen at the IC foundry level, Jisso’s level 0. These would be 3D-SIC with 3D interconnects at the global or intermediate level of the chip wiring hierarchy. Or they could be 3D-IC which interconnects at the immediate chip level.
Finding the 3D technology design sweet spot with the best of power, cost, performance, and content remains a challenge. With IMEC’s recent advancements, the technology has matured and the next step is to provide a clear roadmap for bringing these packages to the marketplace. IMEC engineers are using PathFinding, a virtual design flow process to help optimize and evaluate critical points for TSV alignment, electro migration, yield, and test process steps.