IMEC Research Energetically Stacks Up

LEUVEN, Belgium–IMEC remains on the forefront of research in many areas including nanotechnology, RF MEMS packaging, flip chip, substrates, organic electronics, CMOS-based research, solar cells, and 3D stacked integrated circuits. In 3D stacked packages, IMEC has announced notable achievements.

In October, IMEC engineers demonstrated the first functional 3D integrated circuits (3D-ICs) made by die-to-die stacking using 5µm Cu through-silicon vias (TSVs). Die stacking was done using 200mm wafers in IMEC’s reference 0.13µm CMOS process with added on Cu TSV steps. Before stacking, the top die was thinned to 25µm and bonded to the landing die using Cu-Cu thermocompression. The next stage is to migrate the process to a 300mm platform.

Tests confirmed that circuit performance does not degrade by adding Cu TSVs to interconnect the layers. To evaluate the impact of the 3D-SIC flow on the characteristics of the stacked layers, both top and landing wafers contained CMOS circuits. To see how the stacked 3D layers performed, ring oscillators with varying configurations were distributed over the two-chip layers and connected to the Cu TSVs. These circuits were tested after the TSV stacking process to confirm that the signal does not degrade by the addition of copper TSVs , and these circuits demonstrated excellent integrity. Detailed technical results will be presented at the IEEE-IEDM conference in San Francisco this December.

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“With these tests we have demonstrated that our technology allows designing and fabricating fully functional 3D-SIC chips. We are now ready to accept reference test circuits from our industry partners,” said Eric Beyne, Ph.D., program director, Advanced Packaging and Interconnect Research Center (APIC). IMEC’s program on 3D system integration includes partnering for cost-effective research with several other companies. Equipment and materials suppliers include Applied Materials, Disco, EV Group, ICOS, Lam Research, and NEXX. Other players include Amkor, a SATs provider; SMC, a foundry; ICOS, an EDA supplier; Qualcomm, a fabless company; Panasonic, Intel, NEC, Texas Instruments, ST, and Infineon for logic; and Samsung, Micron, and Qimonda for memory.

Key features of IMEC’s 3D-SIC Cu-nail platform approach includes the realization of a Cu-nail after front-end-of-line (FEOL), but before back-end-of-line (BEOL). It takes advantage of the high-aspect ratio Cu damascene technique as opposed to traditional front-end interconnect via processing, and uses a single litho step. Slightly larger features and pitches and a higher aspect ratio are the result. To accomplish the TSV interconnection, Cu-Cu thermo compression bonding is used with simultaneous polymer bonding.

“Achieving coplanar and particle-free surfaces still presents processing challenges,” said Beyne. New cleaning steps will be included in the future.

IMEC is working with the International Technology Roadmap for Semiconductors (ITRS) and Jisso packaging standards group on 3D technology classification. Beyne added that IMEC proposes a classification of the 3D technology based on the interconnection hierarchy, or the level at which the 3D interconnects are made. The industry is debating terminology and who will perform the interconnection steps for 3D integration


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