IMEC’s vision of next-generation memory

by Katherine Derbyshire, Contributing Editor, Solid State Technology

Nov. 5, 2008 – Over the last several years,the semiconductor industry has focused substantial effort on development of manufacturable high dielectric constant gate stacks for CMOS transistors. High-k dielectrics are needed in order to shrink the gate dielectric’s electrical thickness while maintaining sufficient physical thickness to control leakage. At the same time, the use of high-k dielectrics forces radical changes to the transistor integration scheme. The industry has now established a collection of production-worthy high-k gate stack options. While fabs will adopt high-k processes gradually, research institutions like IMEC are winding down their work in this area.

That’s not to say that future research will ignore high-k dielectric materials — far from it. DRAM and flash manufacturers are aggressively scaling their devices in order to reduce costs. Since memory devices depend on charge storage, they must control leakage and maintain capacitance in order to achieve good performance with physically smaller structures.

In DRAMs, for example, a transition to MIMCAP (metal-insulator-metal capacitor) designs is underway. These sandwich a high-k dielectric between two metal electrodes. As in CMOS gate stacks, the high-k dielectric uses a thicker layer to achieve the same capacitance as an equivalent SiO2-based capacitor. Last year, IMEC demonstrated a baseline MIMCAP process based on TiN electrodes with a ZrO2 dielectric. This year, Serge Biesemans reported at IMEC’s annual press review, the organization achieved an electrical thickness of about 0.5nm with leakage of less than 1×10-5 cm-2 using a SrTiO3 dielectric deposited by atomic layer deposition. Both values are record result, he said.

Flash memory cells face an even more severe challenge. The flash roadmap is the most aggressive of all, as much as three years ahead of logic and DRAM (see Fig. 1). At the same time, flash cells must maintain a stored charge indefinitely. Conventional SONOS (silicon-oxide-nitride-oxide-silicon) flash cells achieve this by placing a nitride charge storage layer between two dielectrics. Charge is injected from the transistor channel, tunnels through the floating gate, and is trapped in the nitride layer. The blocking oxide, between the nitride layer and the gate electrode, keeps carriers from escaping. Here, too, higher density memory requires the use of high-k dielectrics to maintain capacitance while controlling leakage.

Fig. 1: Memory sets the pace in roadmap shrink. (Source: ASML)
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The TANOS structure substitutes TaN and Al2O3 for the gate electrode and blocking oxide, respectively. Further scaling is likely to require more exotic dielectrics and higher trap density in the nitride layer. IMEC’s efforts are focusing on characterization of the trap density and energy spectrum of candidate materials and processes. For example, the trap density of Si3N4 varies with strain. Meanwhile, researchers are considering a wide range of exotic and largely uncharacterized rare earth oxides for use in the blocking layer. Better understanding of such materials as DyScO (dysprosium scandate) and HfLaO (hafnium lanthanate) is a prerequisite for any possible applications in the industry.

Further down the road, it simply will not be possible to store enough charge in a small enough structure. Several candidate non-volatile memories seek to store information using other binary states. Phase change memories depend on a change phase, and therefore electrical resistance, after charge-induced heating. Magnetic memories flip the polarity of magnetic domains. Another promising addition to the list, RRAM, depends on a current-induced resistance change in transition metal oxides such as NiO (see Fig. 2). These are potentially very high-density devices. They do not need thermal or magnetic isolation from each other, and diode-driven architectures should be compatible with 3D device stacking.

Fig. 2: Resistive switching in an experimental metal oxides (MOx) RRAM element. (Image courtesy of IMEC)
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IMEC has announced that it plans to investigate RRAMs further as part of its emerging memory program, with efforts focusing on the switching behavior of the metal oxide-based RRAM cells, and on demonstrating scaling capability down to 25nm. Topics include RRAM stack optimization (including the choice of top and bottom electrode and of the metal oxide), RRAM cell scaling and RRAM integration in a crossbar RRAM array.

RRAMs and other emerging memories are a long way down the road. Even the most aggressive flash suppliers haven’t reached the 2x nm range just yet. Nonetheless, as the ability to print such small features emerges, manufacturers are starting to see what those devices might look like. — K.D.


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