by Julia Goldstein, Ph.D. contributing editor
Speakers at MEPTEC’s Packaging Developments and Innovations Symposium, November 13, 2008 in San Jose, CA, presented various new technologies to enable package miniaturization while keeping costs in check. Much of the focus was on materials innovations that optimize the existing infrastructure. One departure from that was discussions surrounding through silicon via (TSV) advancements.
Craig Borkowski of Henkel Corp. gave an overview of die-attach process options for leadframe packages. Borkowski discussed wafer backside coating (WBC) as an alternative to standard processes where paste or film die-attach adhesives are applied to the package. While additional process steps are required to coat the wafer and cure the adhesive prior to die attach, it can still be a cost-effective method for some products when yield is taken into consideration. For very fine-pitch devices, resin bleed can cause considerable yield loss when using die-attach pastes. WBC adhesives can be formulated with higher thermal conductivity than pastes, which can be critical for applications where heat dissipation is an issue. Borkowski said that at present 95% of leadframe devices use paste die-attach adhesives, while 4-5% use WBC and less than 1% use films. He predicts that use of WBC will increase over the next few years as limited die pad space or high thermal conductivity requirements limit the effectiveness of pastes.
Leadframe packages themselves are changing, and Lee Smith of Amkor described a package designed to overcome performance limitations of existing packages. The new package, with both outer leads and inner lands, increases I/O while reducing footprint compared to a TQFP. Designed in partnership with a customer, the package is designed to meet thermal and electrical performance criteria with no increase in cost.
In his keynote speech on market dynamics, Glenn Daves of Freescale mentioned the importance of partnerships to reduce development costs for individual companies, and noted that this type of collaboration was especially important in development of through silicon via (TSV) technology. The Semiconductor 3D Equipment and Materials Consortium, EMC3D, is doing just that. Speaker Rozalia Beica of member company Semitool showed an example TSV process flow that involved processes done by four different equipment and technology providers. Materials manufacturers would also be involved in process development. Beica described research on optimizing via filling in collaboration with materials companies to adjust plating chemistries for more uniform fill and less oxidation. Because of collaborative efforts, cost of ownership has dropped below $200/wafer, and the objective is to reach $145/wafer by 2009.
Rick Lathrop of Heraeus described dippable solder paste, an alternative to dispensed solder paste. For package on package (PoP) devices, dippable solder can replace tacky flux on the solder balls. It provides a surface that can be attached directly to pads, eliminating the need for solder on pad (SoP) and minimizing the risk of solder ball bridging during reflow. This issue becomes more important as device pitches shrink. Dippable pastes already use powders much finer than traditional dispensable solder pastes, and future directions include even finer powders for pastes that can be used on solder balls as small as 70µm.
Finer pitches and tighter vertical spacing are also driving changes in flip chip technology. Examples include replacing solder balls with columns, eliminating SoP and connecting balls directly to leads, and combining mold and underfill in a single step. As Adrian Murphy of STATS ChipPAC explained, eliminating the underfill step allows for tighter chip-to-chip spacing since a gap is no longer needed to allow space for the dispense needle. This technology can be used for pitches down to 150µm with 50µm vertical gaps.
Miniaturization is blurring the distinction between processes for advanced packages and surface mount devices, and Georges Pascariu of Unovis showed an example where SMT equipment can be used for flip chip and system-in-package (SiP) applications. Traditionally for these applications, one component is attached at a time. By adding wafer handing capability to an SMT die feeder, it’s possible to place as many as eight different components at once. Electronic wafer mapping allows only known good die (KDG) to be selected, and a high-accuracy vision system enables precise component placement.