by Dick James, senior technology adviser, Chipworks
Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.
Dec. 15, 2008 – Sunday at IEDM is always short course day, and this year’s two topics were on “22nm CMOS Technology” and “More than Moore: Technologies for Functional Diversification.” One of the courses is usually a focus on potential technologies for a couple of process generations ahead (e.g., 22nm). This is perhaps looking a bit far ahead, since 45nm is hardly well established yet; Intel and Panasonic have been the only two players until AMD’s recent entrance.
I took in the 22nm course, although there were a couple of sessions in the other I would like to have been at — Tom Lee and Albert Theuwissen are both entertaining speakers, and their respective perorations on RF/analog and CMOS imaging (both pretty hot market segments at the moment) would have been interesting.
The 22nm course was kicked off by the ever-genial Hiroshi Iwai, with a run-through of technology scaling through the lens of the 2008 ITRS. In essence, he detailed the changes to the 2008 update (due out at year’s end), in particular reflecting the slowing rate of scaling that we have seen in recent years, so that at 22nm Vdd, gate length, EOT, and xj will all be larger than predicted in the last ITRS. Correspondingly, the life of bulk CMOS and the adoption of multi-gate devices (MuGFETs) has been pushed out by eight years. And of course the k-value of interlevel dielectrics has slipped again — a bit ironic, since we have just found our first 2nd-gen low-k part using Fujitsu’s nano-clustering silica with a claimed k of ~2.25, putting them ahead of the ITRS prediction.
Iwai finished his talk with his personal roadmap of technologies beyond CMOS, with Si nanowires and germanium or III-V channel MOSFETs being the short-term prospects, and carbon nanotubes, graphene, and other prospects out “in the clouds”. Nanowires are his preference, because of better short-channel effects.
Next up was Kelin Kuhn of Intel, who gave the most amazing review of the challenges in achieving manufacturable 22nm from the device perspective — a hundred densely packed slides in an hour with well over a hundred references. She described the problems caused by increased resistance (SDE and silicides) and fringe capacitances, gave a detailed explanation of mobility and orientation effects, and discussed high-k/metal gate methodology and the pros and cons of planar CMOS vs. MuGFETs/FinFETs. She made one point about MuGFETs that hadn’t occurred to me — essentially they are quantised transistors, since larger transistors have to be made from many units of a single gate crossing the fin substrate, so a whole different modeling regime applies before you even get into the design cycle. At the end of this avalanche of information, Kuhn summarized by saying that 22nm is likely to be planar, evolved from current technology. MuGFETs won’t happen soon; there are just too many risks involved for them to become real in the next five years.
After lunch, Geert Vandenberghe from IMEC discussed the lithography options, covering wet lithography and EUV and the associated problems with mask and reticle design and manufacture. He also went through the different types of double masking and patterning — although strangely absent was the subtractive double patterning practiced by Intel, in which gates are first patterned as continuous parallel lines and then cut into dummy and functional segments by a second etch mask.
Jeff Gambino of IBM gave a good overview of the BEOL challenges, taking it beyond the usual problems with super-narrow lines and super-fragile low-k dielectrics, also discussing air-gap techniques, packaging including TSVs, and reliability problems.
Finally, Purdue University’s erudite academic Kaushik Roy reviewed device and circuit interactions. The inherent variability of processing and structures at nodes 45nm and below can make device operation unpredictable, never mind the increased leakage. He detailed some of the circuit techniques used to mitigate the problems, such as high- and low-Vt transistors, gated blocks of memory, and the like. Some of them have been around for a while, but the need at 22nm becomes even greater. Judging by some of his slides, he’s been working with Intel, and the comments on dual-Vt made me wonder if his work had an input into Intel’s SoC/Dual Vt paper to be presented on Wednesday.
By that end of the afternoon we were getting punch-drunk with an excess of information, but all in all, a good and informative day. I do have some criticism for the facility side of the course — too many of us crowded into too small a space, I gather there were over 300 attendees — and the coffee ran out! Not quite as bad as sitting in a full 747, but getting there.
For my money, Kelin Kuhn gets the Data Density of the Day award (definitely not a criticism); hers was an extremely well-structured talk, though most people would have taken a full morning to deliver it! Now for the conference proper. — D.J.
DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected], www.chipworks.com.