IEDM Day 2: Brain cells, “stress,” nanowire batteries

by Dick James, senior technology adviser, Chipworks

Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.

It’s hard to discuss the Monday morning plenary sessions without getting a bit linear. First up was Peter Fromherz from the Max Planck Biochemistry Institute in Munich, talking about interfacing chips with brain cells. That sort of topic usually makes my eyes roll up, but he actually had some good pragmatic stuff. Question: How do you monitor brain cells without affecting them? Answer: Lay them on a transistor gate so that the voltage pulses turn the transistor on, and measure the response.

Similarly, to put a voltage pulse into a cell without contaminating it, you lay it on a capacitor with a physiologically inert HfO2 or TiO2 dielectric, and pulse the capacitor. The actual link between the cell and the inorganic devices relies on the response of the ions within the electrolyte containing the cell and device, influencing the ion channels that are the communication media of nerve cells. All the semiconductors have a passivation layer so that the electrolyte does not affect the chips.

Fromherz had an impressive video of a slice of brain laid over an array of transistors, showing how a pulse at one point influenced the neurons and was transmitted through the tissue, its movement monitored by the transistor array. A bit simplistic — as well as a bit gruesome — but a good example of how basic research could lead to the prosthetics of the future. The blind may yet see, if this kind of experiment pays off.

Stefan Lai, formerly of Intel, then Ovonyx, and now independent, gave a review of non-volatile memories, working his way through NOR and NAND flash to cross-point memories such as the SanDisk/Matrix, to his recent phase-change memories and IBM’s Millipede MEMS-based system. Asked when PCM would appear in a real product, he declined to comment — but given the list of pros and cons (mostly cons) for PCM he had shown earlier, it doesn’t look any time soon.

As the session stretched into numb-bum time (there are no morning or afternoon breaks at IEDM, and three hours is a long time to sit in a conference room), Tatsuo Saga of Sharp gave a good review of the PV options (though at times a little sales-pitchy and promotional). One surprising stat: some of the more complex solar cells are now closing in on 40% conversion efficiency.

Having just installed geothermal heating at home, he had me thinking about solar PV as well — not an obvious thing for Canada where I live, but Ottawa is actually south of a lot of the installations in Germany, which has gone gung-ho for renewable energy of all sorts. Unfortunately, now that fossil fuel prices have fallen off a cliff, the economics have changed and the payback time will be a lot longer — exactly what torpedoed the solar movement back in the ’80s.

On the way out of the hall for lunch I crossed paths with Stanley Wolf, author of what is still the most comprehensive set of reference books for the industry, “Silicon Processing for the VLSI Era” — now a slightly quaint title, since time has gone by since they were first launched. I mention this because Stan is thinking of updating volume 1, last revised in 2000, and needless to say quite a lot has happened since then in chip processing. Keep an eye on his Lattice Press Web site to see when the new version comes up.

Afternoon sessions

The conference proper started in the afternoon with the usual irritating plethora of parallel sessions. The AMD/IBM/Freescale alliance gave a paper on embedded carbon-doped epitaxial source/drains to stress nMOS transistors (paper 3.1), which gave a decent 9% Ion increase over the equivalent device using nitride + memorized stress. Unfortunately good epi growth requires low-doped drain extensions, so there is still work to do to get the technique integrated, increased series resistance is not a price we want to pay.

This was followed (3.2) by an examination by Fujitsu of the mechanism of the stress memorization techniques (SMT). The gate polysilicon is amorphized by implantation, then capped with nitride. During the source/drain anneal the amorphized silicon expands as it re-crystallizes, but since it is constrained by the cap and sidewall spacers (SWS), compressive vertical stress is applied to the channel underneath. After the anneal the nitride cap is removed, and a conventional contact etch-stop liner (CESL) used to apply lateral tensile stress. We tend to think of nMOS stress as only needing to be tensile, but in the z-direction it’s compressive stress that helps for both nMOS and pMOS.

Figure 1: Effect of channel stress on nMOS & pMOS transistors. [1]

As part of the investigation, arsenic and phosphorus source/drain implants were tried, and oxide and nitride sidewall spacers. As would be expected, the harder nitride SWS is more effective at applying stress to the channel, and possibly the greater atomic mass of the arsenic increases the expansion tendency of the gate polysilicon.

Figure 2: Effect of SMT on electron mobility. [2]

Then we got into one of those timing clashes that IEDM is notorious for — two interesting papers in different sessions at the same time! Both by Intel, as it happened, one on CMP and the other on the use of (110) silicon — I picked CMP, since the Intel 45nm metal gate structure would not have been manufacturable without a highly tuned CMP capability.

That was the message from Joe Steigerwald (2.4), and it jives with our analysis when we looked at the structure. CMP is used to polish back the surrounding dielectric to expose the sacrificial poly gates (POP step), to polish down the final metal fill and electrically isolate the metal gates, and of course for all the copper levels in the BEOL. This is complicated, and arguably helped, by the density of the real and dummy gates — see our pictures below.

Figures 3-4: Intel’s metal gates in cross-section and plan-view. (Source: Chipworks)

If you look at the structure, we can see that under-polish at the POP step will not expose the poly for removal, and over-polish could get into the raised epi pMOS source/drains. Similarly under-polish at the metal removal could leave gates shorted together, and affect the contact etch yield, and over-polish will leave them too thin and high-resistance, especially pMOS if too much of the Al-Ti fill is removed. One thing not mentioned is the thin layer of AlTiO on the top of the gates, presumably a side-effect of the CMP — or are they using E-CMP (electrochemical CMP)?

The standing-room only paper of the afternoon was an invited paper given by Yi Cui of Stanford, on nanowire batteries — they are doing some really interesting work on using silicon nanowires to replace graphite as the anode in lithium-ion batteries. Bulk silicon has good performance, but limited surface area, and expands too much as charge is stored to be a practical device. With nanowires there is of course much greater surface area, and room for the nanowires to expand. The bottom line is that there is potentially as much as ten times as much charge storage capacity as the equivalent conventional Li-ion battery. They are also working on LiMn2O4 nanorods to improve cathode performance, and getting encouraging results. After the plenary session on solar, which requires the extensive use of batteries if you want to go off-grid, this paper appeared to strike a chord with attendees; there was great enthusiasm for this work.

In the evening was the reception, a good chance to catch up with colleagues, and confirm that engineers and scientists are the same as normal folks — give them food and wine, and you need ear protection after a while! — D.J.


[1] S. Thompson, et al, A 90-nm logic technology featuring strained-silicon; IEEE Transactions on Electron Devices; Volume 51, Issue 11, Nov. 2004, pp. 1790 — 1797.
[2] T. Miyashita et al, “Physical and Electrical Analysis of the Stress Memorization Technique (SMT) using Poly Gates and its Optimization for Beyond 45nm High Performance Applications,” Proc. IEDM 2008, pp. 55-58.

DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected],


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