IEDM Day 3: SRAMs, image sensors, flash memory

by Dick James, senior technology adviser, Chipworks

Editor’s Note: Each day during IEDM, Chipworks’ Dick James will share his thoughts on what he saw as the best presentations.

Dec. 17. 2008 – Today was a bit of a researchy day, with a predominance of more academic or blue-sky papers. Consequently I tended to bounce around a bit without a real focus, everything from SRAM to image sensors to radiation soft errors in flash memories.

The IBM Common Platform group started the day (paper 10.1) with a 32nm high-k/ metal gate SRAM paper, actually a scaling study that went under the radar of the conference pre-publicity of dueling 32nm SRAM sizing. IBM’s Wednesday paper details a 0.157μm2 cell, TSMC has a 0.15μm2 cell, and Intel a 0.171μm2 cell.

Here we have an analysis of a series of 0.149μm2, 0.139μm2, and 0.124μm2 cells, fabbed in a low-power process with double patterning for gate and double masking for contacts. The HK/MG gives a reduction in the effect of random dopant fluctuation which decreases threshold voltage mismatch, and also drops gate leakage, enabling functional SRAMs down to 0.124μm2. Adding a dual ground to the cell write assist also improves the voltage range and soft fail rate of the smallest cell, at what space penalty is not disclosed.

Chipworks has been focusing on image sensors for a while now, so Rohm’s announcement of a CIGS on CMOS sensor (paper 11.2) caught my attention. CIGS (copper indium gallium selenide) is one of the hot materials in the PV field, so the idea of using it for an image sensor is not that far off the wall — the big problem has been high dark current.

Rohm gets around this by using a double layer of zinc oxide as the top blanket electrode. One layer is semi-insulating ZnO, and the top sub-layer is Al-doped to give conductivity; this has the dual advantage of isolating the pixels and reducing dark current. The CIGS is co-evaporated on to a molybdenum base layer/back contact (which contacts the top metal layer of the CMOS scanning chip below), with a CdS buffer layer under the ZnO bi-layer.

Figure 1: CIGS photodiode structure. (Source: Rohm)

Figure 2: CIGS image sensor structure. (Source: Rohm)

The pixels are 10μm × 10μm in a 352 × 288 array, so this is clearly a proof of concept. The sensitivity can be extended to sub-lux illumination levels by biasing the photodiode to induce avalanche multiplication. Since the photodiodes are on top of the die, they have an aperture ratio close to 100%, and this coupled with the CIGS spectral response extending into the near-infra-red makes the sensor suitable for automotive and security applications.

In the same session Samsung compared 1.4μm frontside- and backside-illuminated (BSI) sensors (paper 11.4). BSI sensors have been getting publicity of late, since the continuous drive for multi-mega-pixel phone cameras have driven pixel size down to the point where it’s difficult to get enough light in to a frontside pixel. If you thin the wafer down so that the photodiode can go on the backside, then the aperture ratio is not limited by the metal stack on the front.

Figure 3: Frontside (left) and backside illuminated sensor structures. (Source: Samsung)

As expected, the BSI sensor had impressive performance compared with the frontside version, and Samsung claims that the technology will extend pixel size down to ~1μm. I guess that will give us the dubious (for me) societal benefit of a 10-megapixel cameraphone.

By coincidence, we at Chipworks are now examining Sony’s 1.4μm-pixel, 8-Mp chip — I’ll have to compare them when I get back to the office!

Another interesting paper (14.6) by Numonyx and a bunch of European universities discussed a joint study on potential neutron-induced soft errors in flash memories. They took a number of 4GB and 8GB chips and irradiated them to induce loss of data.

And neutrons do create data loss — not necessarily at the level where it cannot be corrected by the built-in ECC that’s on every chip — but the trend is in the wrong direction, since denser memories and smaller feature size have higher data loss. This made me think of the latest flash memories that we have looked at, with a BPSG interline dielectric in them. Boron has a high neutron cross-section, so any chip with BPSG in it is a bit more vulnerable to neutron-induced soft errors.

Figure 4: TEM cross-section of storage cells in 6GB flash memory. (Source: Chipworks)

Having said that, the statistics shown in the paper indicate that for every GB in the chips they tested, you may lose up to 60 bits if you spend 27 years at airline cruising altitude, depending on which flash chip you’ve got in your thumb drive. Given that these things are used for dumb storage anyway, will you actually notice 60 bits missing from that 8MB picture in your phone? All the same, a nice piece of research.

Renesas had a paper (18.1) that will have me bugging our TEM guys back in the office, since they’ve been mapping transistor strain using the acronym-laden LAADF-STEM technique (low-angle annular dark field scanning transmission electron microscope). This actually looks as though it might work, but you have to be able to do convergent beam and have the LAADF detector, and use a thick ~2500A sample.

Wednesday is the heavy stuff at IEDM — multiple papers on 22nm, 32nm, 40nm, and 45nm from the big guys. More tomorrow! — D.J.

DICK JAMES is a 30-year veteran of the semiconductor industry and the senior technology analyst for Chipworks, an Ottawa, Canada-based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. Contact him at 3685 Richmond Road, Suite 500, Ottawa, ON, K2H 5B7, Canada; ph 613/829-0414, fax 613/829-0515, [email protected],


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