IEDM: IMEC optimizes 65nm Ge pFET

by Debra Vogler, senior technical editor, Solid State Technology

Dec. 15, 2008 – At IEDM this week, researchers at IMEC reported that minimizing the Ge in diffusion into a silicon capping layer is the key to boost electrical performance and reach 1nm EOT (equivalent oxide thickness) devices (paper #35.5, “Record Ion/Ioff Performance for 65nm Ge pMOSFET and Novel Si Passivation Scheme for Improved EOT Scalability,” J. Mitard, et al.). The group reported achieving an Ion = 478μA/μm and an Ioff,s + 37nA/μm at a Vdd= -1V in a 65nm Ge pFET. This performance was achieved, they say, through better control of the Ge in-diffusion using a low-temperature epi-silicon passivation process.

The group accomplished short channel control using a doping optimization scheme of Si CMOS at 65nm (i.e., halos, LDD and HDD). Regarding external resistance engineering, the researchers discovered that the reduction of NiGe thickness down to 5nm gave the best trade-off between low external resistance and voids contribution.

Figure 1: Schematic model to illustrate, in terms of defects, the difference between the two epi-silicon processes. (Source: IMEC)

Key to boosting intrinsic performance was gate stack passivation, particularly lowering the silicon passivation layer deposition temperature. The group found that lowering the silicon deposition from 500°C to 350°C dramatically reduced the Ge incorporation in the silicon capping layer and the Ge segregation to the top interface of silicon. The paper noted that Ge incorporation in the silicon passivation layer has a strong impact on the electrical measurements (see Figure 1).

Figure 2: Ion vs. T (Si-500°C). Narrow process window (~8 monolayers) to reach the optimum Ion performance. (Source: IMEC)

It was also found that Ion depends strongly on the capping layer thickness (see Figure 2) with a maximum in Ion occurring at 8 monolayers. Shifting even one monolayer from the optimum value led to an ~10% lower drive current. Vt control was also found to depend strongly on the chosen silicon thickness (see Figure 3). — D.V.

Figure 3: Sub-threshold swing at low VDS vs. Vt for epi-silicon process @ 500°C. Vt is fully uncontrolled and a trade-off has to be found in T(SI) between low SS and low Vt spread. (Source: IMEC)


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