IEDM: SEMATECH optimizing advanced gate stack for 22nm low-power apps

by Debra Vogler, senior technical editor, Solid State Technology

Results of a study slated to be discussed by SEMATECH researchers at this week’s IEDM highlight the importance of the process sequence on performance, variability, scaling, interface quality, and reliability for LaOx capped HfSiON/metal gate structures (“Device and Reliability Improvement of HfSiON+LaOx/Metal Gate Stacks for 22nm Node,” J. Huang, P.D. Kirsch, et al.). The group found that an SiON interface layer (IL) is a valuable scaling aid with leakage current (Jg) >200× lower than with an SiO2/polySi IL. Reduced La diffusion to the IL, they note, is what enables an SiON IL to prevent performance degradation.

By optimizing the process sequence, the LaOx cap thickness, and the SiON IL, the researchers were able to address PBTI (positive bias temperature instability) and mobility degradation issues of a low Vt HfSiON+LaOx gate stack. A high Ion/Ioff (1250μA/μm/100nA/μm) performance of 0.31 Vt,lin nFETs was achieved without using a strain booster. The group concludes that such a gate stack is realistic for 22nm node LOP (low operating power) applications.

The group noted that previous work (S. Kamiyama et al., IEDM Tech. Dig., p. 539, 2007) had shown that, although Vt was low when using an SiOn/HfSiON+LaOx stack with 0.68nm EOT at 32nm half-pitch, Ioff was too high for the 22nm LOP application.

This type of gate stack is of interest to the logic community, particularly the low standby power and low operating power communities, according to SEMATECH researcher Paul Kirsch. “The reason we focused on low operating power is that we were able to meet both the gate current density and equivalent oxide thickness for that particular product offering,” he told SST — though, he added, “That’s not to say that it’s inappropriate for the high performance applications.”

Figure 1: Nitridation process sequence affects Vt tuning ability. Maximum Vt tuning is ~700mV. (Source: SEMATECH)

Figure 2: Mobility is degraded with LaOx thickness and nitridation process. (Source: SEMATECH)

A basic problem the industry has encountered, Kirsch explained, is a mechanistic understanding that a small amount of nitrogen in the bottom IL is quite beneficial over an SiO2 IL. However, there had not been the same understanding with respect to a high-k LaOx capped metal gate stack. Previously, the semiconductor community had put the LaOx on top of the high-k dielectric and it was done without understanding the nitridation process sequence. In the current SEMATECH paper, the data shows that with the SiON IL, the bias temperature instability reliability and the transconductance metrics are improved as is the amount of Vt tuning with the SiON IL, which is not possible with the SiO2 IL. “What we’ve shown here (see Figures 1, 2) is that it’s actually beneficial to put the LaOx cap down before doing any nitridation,” Kirsch told SST. “We’ve seen an advantage in the amount of Vt tuning and in the high-field mobility we can achieve.”

Figure 3: Ion/Ioff performance of 0.31 Vt,lin nMOSFET with 0.74nm EOT. (Source: SEMATECH)

According to Kirsch, the Ion/Ioff improvement achieved by the group (Figure 3) suggests that the industry will be able to scale down to ~0.7nm and continue to see Ion/Ioff benefits. Additionally, the researchers’ were able to achieve a Vt uniformity (Figures 4, 5) that is equal to a little better than 30mV across the wafer, which, Kirsch noted, is typically a metric of manufacturability of the technology. — D.V.

Figure 4: Optimized LaOx cap process type reduces Vt variation. (Source: SEMATECH)

Figure 5: Optimized LaOx cap process sequence reduces Vtvariation. (LBN = LaOx capped before nitridation; LAN = LaOx capped after nitridation.) (Source: SEMATECH)


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.