Intel decloaking 32nm logic tech at IEDM

by Debra Vogler, Senior Technical Editor, Solid State Technology

Dec. 15, 2008 – Intel’s 32nm logic technology will be described in a paper to be presented at the IEDM conference this week by Sanjay Natarajan, the company’s director of 32nm CMOS technology development. Featuring second-generation high-k/metal gate (HK+MG) technology, the transistors have a 9Å EOT (equivalent oxide thickness) high-k gate dielectric, dual band-edge workfunction metal gates, and 4th generation strained silicon. The transistor gate pitch is 112.5nm with a feature size scaling of ~70% and an area scaling of ~50% compared to Intel’s 45nm technology. Immersion lithography (193nm) was used for critical patterning layers.

According to Natarajan, compared to Intel’s 45nm technology, the transistor drive currents for the 32nm process are ~14% higher, and transistor switching speed is improved >22%. The technology was proven on a high-density 291Mbit SRAM test vehicle with a 0.171μm cell size (>1.9 billion transistors), which was fabricated using all 32nm process features.

The company has reported that its 32nm logic technology is on track for high-volume manufacturing in 4Q09. — D.V.


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