by Bob Haavind, Editorial Director, Solid State Technology
Dec. 16, 2008 – New memory concepts and the latest 32nm CMOS with metal gates and high-k dielectrics were highlights of the 2008 International Electron Devices Meeting (IEDM) in San Francisco, Dec. 15-17. A wide range of innovative device technology, including 3D wafer-level integration and a nanowire battery were also presented.
Rapid improvement in memory, especially flash memory now so widely used in digital cameras, notebook PCs, and other mobile devices, was described by Stefan Lai of Being AMC (formerly with Intel) in a plenary talk. He cited work to push flash toward 32nm and beyond, including the TANOS process from Samsung which incorporates a charge-trapping layer rather than a floating gate to minimize cell-to cell coupling, thus solving short channel effect problems. Another advancement from Kinam Kim from Samsung was the hemi-cylindrical FET where channel length extends above the planar silicon surface with the TANOS charge-trapping layer wrapping around. This will allow flash to be scaled down to sub-32nm nodes, Lai said, but at these sizes NAND flash faces a bigger challenge. Only a few hundred atoms are in the charge-trapping layer, and in a multi-layer cell (MLC) only tens of electrons separate storage layers. With leakage during cycling, these few electrons will quickly be depleted, which may be OK for some consumer uses, such as memory cards for cameras, but not for the solid-state disk (SSD) in servers, Lai pointed out.
Nevertheless, Lai expressed confidence that innovative memory advances would push beyond such barriers, like some being reported at the 2008 IEDM. He cited previous work on 3D NAND layers on a single chip by Samsung, Macronix, and Toshiba, using shared lines and making a whole stack of control gates in a single step in Toshiba’s bit-cost scaleable flash. Crosspoint memories can be stacked in 3D, but process temps must be kept within limits as each layer is added, Lai pointed out. If pushed beyond 400°C, tungsten may have to be used instead of copper lines, for example.
Lai cited work being reported by SanDisk and Toshiba at IEDM 2008 to enable what they call “super multilevel NAND flash” — still using a floating gate, but with tight Vth and sheet resistance control to push this technology to 32nm and beyond.
One solution to charge retention problems is to “get away from a charge storage transistor altogether,” Lai said. Device resistance may be changed by applying an electric field or current, he pointed out. A stack-friendly all-oxide 3D RAM, or resistance RAM, was reported by M.-J. Lee et al of Samsung, for example. It uses a GaInZnO peripheral TFT using low-temperature processing steps demonstrated by fabricating the devices on glass substrates. A specialized stacked-memory structure in a cross-point grid minimizes chip real estate.
A more exotic approach is a carbon-based resistive memory technology reported by Frans Kreupl, et al of Qimonda. The group demonstrated feasibility for resistive memory elements of graphene-like conducting and insulating carbon as well as carbon nanotubes. This report was part of an entire IEDM session devoted to work on graphene and carbon nanotube devices.
Most likely to reach commercial production first, however, according to Lai, are phase-change memories. In a PCM device, switch current from an electrode to a chalcogenide material heats the region around the contact, which makes it amorphous or high-resistance, and quenched to make it crystalline, or low-resistance. Study of such factors as retention loss and transient effects of delay, switching, and recovery, were reported at this year’s IEDM as these devices evolve toward smaller structures and tighter pitches to make them commercially competitive.
Lai suggested that these exotic multilayer memories require repetitive processing that may need only 10-15 process tools, so this might be done in a minimal fab while the layer of complex circuitry for drivers and read sensors might be farmed out to a foundry. He also pointed out that in memory there is no such thing as “perfect data,” so new system approaches may have to evolve to deal with defects. He cited work by Systems Genetics Inc., Longmont, CO, that uses a special processor and compensation engines in a systems approach to double capacity gain and greatly boost endurance for advanced NAND devices.
The hard-disk drive (HDD) field has a larger toolbox to deal with imperfect or noisy data, and their techniques might be adapted in future multilevel memories, according to Lai.
Three-dimension (3D) chip integration using through-silicon vias (TSV) also was an important topic at IEDM, including a report on a wafer-level scheme reported by F. Liu, et al of IBM. It incorporates 25μm TSVs with 17:1 aspect ratio drilled by RIE with tungsten interconnects. Lock-and-key structures ensure that there is no lateral shift between wafers during a hybrid copper-adhesive bonding step.
A novel multichip module integration approach using self-assembly with defined hybrid hydrophobic areas and liquid evaporation for positioning chips was reported by T. Fukushima et al of Tohoku U. in Japan. It achieved about 400nm alignment accuracy.
Nanowire battery technology for next-generation electronics was reported by Yi Cui, et al, of Stanford U. Energy density for batteries has been advancing only about 8% a year thanks to packaging improvements, but this is reaching limits so new concepts are needed, Cui reported. The graphite anode in lithium batteries has very limited charge storage capacity, but higher capacity materials like silicon or germanium swell too much during alloying in bulk materials. Nanowires, however, offer an alternate approach. Studies of potential nanowire structures showed most promise for lithium inserted into silicon nanowires, but there is a problem keeping the silicon crystalline through charging cycles. The group has devised nanowire structures in which a silicon core remains crystalline under constant charging for 145 cycles with 95% charge retention, and offering about 6× the storage capacity of carbon, which shows promise for commercialization, according to Cui. The group developed a CMOS-compatible process to fabricate these silicon-lithium nanowires for on-chip power sources.
Among reports on 32nm second-generation high-k metal gate (HK+MG) CMOS logic was a late paper by S. Natarajan et al, Intel, with enhanced channel strain, which achieves the highest drive current yet for nMOS. Another late paper by NEC reports a cost-effective approach to a 32nm CMOS platform using advanced single-exposure lithography with custom illumination to avoid the extra steps of dual exposure and double patterning. A gate-first HK+MG process was described.
Despite the weak economy, attendance for the conference remains fairly high, with over 300 attendees to the Sunday short course on 22nm CMOS technology, for example. — B.H.