The 3-D Brawl
This month’s 3-D symposium at the MRS Fall Meeting showed that 3-D, whether based upon through-silicon via (TSV) or one of its rivals, has entered a new stage — brawling. This is encouraging. Laboratory technologies, like newborn babes, require the full attention of their owners. It isn’t until the newcomers creep out of the lab to face their rivals that conflicts begin. By next December, some winners should be in production. The symposium’s six sessions, devoted to “Materials and Technologies for 3-D Integration,” covered integrated processes, vias, plating, wafer thinning, bonding, and applications.
Many choices must yet be made to reach integrated manufacturing. These include where (front end or back end), when (beginning, end, or somewhere in between), how (drilling, plating, thinning, bonding, packaging) and why (lower cost or higher performance) manufacturing should proceed. All of these topics elicited differing opinions and contrasting recommendations somewhere in the 45 or so papers.
The opening survey paper by Fraunhofer IZM presented an overview of 3-D process requirements and challenges. It concluded that many individual processes have been demonstrated, but the critical infrastructure elements have yet to be brought together to achieve acceptable time to market, cost, reliability, and performance for volume production.
A typical choice is between stacking wafers on wafers, versus stacking singulated die on wafers. MIT Lincoln Labs reported their wafer on wafer stacking of fully fabricated SOI wafers. Others voiced good reasons to assemble die on wafers. SUSS Micro Tec, who sells equipment for both approaches, suggested both: die-on-wafer to avoid differences in die sizes, wafer sizes, and KGD yields in mixing CMOS with other technologies; wafer on wafer to maximize throughput and minimize cost in homogeneous integration of high-yield devices. Pay your money and take your pick!
TSV dominated the interconnect choices. However, even TSV advocates are split between those who prefer high-aspect ratio vias to minimize wafer thinning, and those who prefer additional wafer thinning in exchange for lower-aspect vias. A Bosch presentation on the history and success of the widely used deep reactive ion etch ( “DRIE” or “Bosch” process), was followed by a paper from Xsil advocating diode-pumped solid-state laser drilling as a faster and simpler way to open fine-pitch vias for plating.
Plating itself presented many variations. Those of us unfamiliar with plating think of it as a simple process: mix up a proper bath, turn on the switch, and on it goes. Semitool provided a concise education in the complexity of deep via plating. The problem is to uniformly fill the vias from the bottom up without voids, despite the dynamic changes occurring during deposition.
Semitool’s plating solution (pun intentional) is precise control of the bath components, and continuing adjustments of the electrical current. They find that each wafer type requires a unique recipe, based upon the number of vias, their size, and their pattern density.
IMEC identifies uniform filling of the vias as only part of the problem; reducing the plating time while maintaining void-free quality is the real challenge. IMEC also reported statistical comparisons of four common thinning methods (rough grinding, fine grinding, CMP, and plasma etch) on silicon wafer strength. A major unexpected conclusion is that the grinding mark orientation plays a key role in determining resulting wafer strength.
CEA-Leti presented daisy-chain testing results statistically relating plating process parameters to the electrical performance of the resulting TSV. Their test vehicle vias are 3 to 5µm in diameter and 12 µm long, on 30µm pitch. They achieved yields above 90% for daisy chains with 3,200 TSVs.
STMicroelectronics has developed thin silicon film layer transfer as a solution for deep submicron-diameter via layer interconnections. Monolithic integration with sequential processing avoids the limitations that prevent alternative current approaches from addressing these dimensions.
Ziptronix reported extension of their proprietary Cu-Cu direct bonding technology to 1.5 µm pitch. The planar oxide bond technology requires only simple alignment and placement to bond wafers or die which have received a suitable surface activation.
In conclusion, these clashes of ideas are a vital step in developing integrated manufacturing for 3-D assembly. I look forward to hearing from the survivors next December.