(January 29, 2009) TOKYO &#151 Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices, including mobile terminals and PCs. The leadframe enables semiconductor packaging with a thickness of 0.15 mm, approximately 1/20 the thickness of existing general products, according to the company.

The new packaging developed by DNP differs from existing formats created by mounting the IC chip on top of the leadframe. DNP has established a technology that leaves only the necessary circuit portion of the lead frame, removes the plate mounting for the IC chip, and, in cases where it is structurally necessary, etches the leadframe portion used for mounting the IC chip into a concave shape, into which the IC chip is then embedded. By downsizing not only the leadframe, but also slimming down the IC chip and mold to the maximum possible extent, it has become possible to create a semiconductor package that is significantly thinner than previous generations of devices.

The precision of the plated area has been improved by roughly three fold to ±0.050 mm from the existing ±0.150 mm, and it has also been possible to achieve improvements in humidity reliability at the same time.

The 0.15-mm package.

In line with the shift to more compact and increasingly high performance in a variety of electronic devices, including mobile PCs and mobile phones with PDA functions, there has been a sharp pick up in demands for downsizing, slimming down, and densification of semiconductor packages, DNP explains, adding that 3D packaging also is experiencing an uptick in demand. These include 3D packages that multi-layer the semiconductor packaging, package-on-package (PoP); and those that multi-layer the IC chips, die stacking.

In the case of multilayered-IC-chip semiconductor packaging; while it is relatively easy to achieve a slimming down of the overall package, given that it is the IC chip itself which is multilayered, other issues remain, including the fact that it is not easy to assure the quality of each individual multilayered chip (determining known good die or KGD), and also of declining yields. As a result, DNP considered the multilayered semiconductor package type, where the quality of the IC chips can be screened on an individual basis, to be the optimum type for its purposes, and has developed a lead frame for use with the slim molded semiconductor package.

The leadframe with an embedded IC chip and high-precision plating developed by DNP completed U.S. patent registration in July 2008, with Japanese patents pending. The company will also exhibit this lead frame at the DNP booth (West 6-14) at the NEPCON WORLD JAPAN (the 10th PRINTED WIRING BOARDS EXPO) to be held at Tokyo Big Sight from January 28.

For more information, visit www.dnp.co.jp.