Jan. 5, 2009 – NEC Corp. says it has developed and demonstrated an operating nonvolatile magnetic flip-flop, opening the possibility for SoCs that require zero power in a standby state and can be quickly returned to an active state.
The magnetic flip-flop (MFF) is produced by integrating data flip-flop (DFF) with magnetic tunnel junctions and some circuitry to switch the direction of the junctions’ magnetization. The MFF operates on the same voltage as existing flip-flops, so it can be used as a library tool for automatically laying out SoC designs, NEC says in a statement. During normal operation it operates at the same 3.5GHz frequency as DFFs, so the magnetic tunnel junctions don’t affect MFF clock frequency. Plus, the junctions can carry out MFF functions if power is lost. The junctions were created using the same process as ones for a 250MHz high-speed MRAM, with layers incorporated into an intermetal oxide layer making it easier to integrate both MFFs and MRAMs into one SoC.
Electronic devices increasingly need to balance lower power consumption in higher-functionality devices. One way to reduce SoC power consumption is eliminating power usage when in inactive mode, but it’s not easy to reduce standby current b/c cutting all power to the SoC could cause data loss in the logic circuits built with CMOS gates. Replacing DFFs with MFFs and volatile SRAMs with nonvolatile MRAMs can make an SoC nonvolatile, and facilitate the design of standby-power-free SoCs, the company notes. FeRAM technology addressing the DFF side is already being used but with limited write cycles, and SoC operating voltages of ≤1.2V are too low for the FeRAM to be appropriately controlled, so FeRAM-based nonvolatile flip-flop DFF to be used as a library tool for automatically laying out SoC designs. The new MFF technology, the company says, shows how to use MFFs and MRAMs requiring ≤1.2V with unlimited write endurance.
Figure 1: Die photo. (Source: NEC)
NEC says it plans to keep working on such technology applying magnetic tunnel junctions to SoCs, with the goal to demonstrate an SoC integrated with MFFs. The research is partly supported by Japan’s New Energy and Industrial Technology Development Organization’s (NEDO) MRAM technology development project, which aims to produce high-speed nonvolatile memories embedded in system LSIs.
Figure 2: MFF circuit diagram. (Source: NEC)