NEC: Trumping conventional scaling with 3D packaging

by Debra Vogler, senior technical editor, Solid State Technology

In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC). The new SoC’s architecture consists of separate logic (excluding embedded memory cores) and memory chips (chip-stacked flexible memory) that are closely stacked. The company presented results of its development work at the International Solid-State Circuit Conference (ISSCC) 2009 (San Francisco, CA, USA, Feb. 8-12).

Although 3D packaging technology is now applicable to multi-stacked general-purpose DRAM, multi-stacked flash memory, and small-packaged imagers, there is no suitable 3D packaging technology application for SoC, according to Yasunori Mochizuki, GM of NEC’s device platforms research laboratories. The company anticipates that by developing these technologies, new applications using 3D packaging will come about to realize large-scale SoCs.

Embedded memory area reduction cannot enjoy the benefits of traditional scaling because of process variations, Mochizuki told SST. Additionally, the required embedded memory size increases more rapidly as the logic size (number of logic gates) increases.

The chip-stacked flexible memory developed by NEC is a third kind of memory that features both fast access in the embedded memory and large memory size in the general-purpose memory. It also enables dynamic memory allocation during LSI operation that is effective for an SoC’s multiple functional IP-cores (functional blocks), thereby reducing SoC design and fabrication costs. These features are enabled by having separate logic and memory chips — memories are placed on top of the logic IP cores, as well as network-on-chip (NoC) technology and 3D packaging.

According to Mochizuki, flexible memory configurations are enabled because the NoC connects the multiple memories to each other through an interconnect on-chip network that determines how memory tiles are bundled and assigned to logic.

The chips containing the “flexible memory” and logic chip are stacked closely (3D packaging) by using multi-layered LSI wires that are connected without solder-ball bumps. This type of 3D packaging allows for a chip gap to be in the sub-micron range and the wire pitch to be as small as 10μm. — D.V.

Chip-stacked flexible memory chips (top) and logic-chip (bottom). (Source: NEC)


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