SPIE tracks the tightening litho horse race

by Griff Resor, Resor Associates, SST editorial advisory board

Experts say we’re on an ‘optics forever’ path, but EUV is gaining momentum and closing the gap, though the finish line is still several years away (and may keep moving). This year’s SPIE’s Advanced Lithography Conference in San Jose, CA, provided a detailed update on what is becoming a tight horse race.

The 32nm node is going into production now, with 193nm immersion optics, double patterning, improved overlay, and a bunch of new processes and materials. In two years the 22nm node will move into production; most expect this node will be done with yet another extension of optical lithography. It is clear, though, that if EUV were ready now, many process engineers would like to use it. C.K. Bok of Hynix was quite frank: “I want to use EUV [for the 22nm node] but my boss makes me work on optical lithography too, because EUV might not be ready and we have to have a solution.”

The ‘optics forever’ story

ASML, Canon, and Nikon continue to improve their 1.35 NA optics, providing improved polarization control through the projection lens, and new layers of feedback to control lens heating. Brion introduced software to analyze each mask and generate “source-mask co-optimized illumination”, a technique that increases the process window at 32nm by over 40%. Excimer laser bandwidth and speckle are being understood at levels of perfection formerly neglected because they add only a few nanometers of error. These improvements now provide an adequate process window for the 32nm node.

Which form of double patterning technology will be most widely used at the 32nm node is not clear. Spacer technology may provide better-defined structures (because chemically amplified resist can be replaced with smoother edged material) and does not require as tight a tolerance for overlay — but spacer technology appears to be more expensive. Suppliers of resists are developing coatings and/or process steps to “freeze” (harden) the first resist pattern so that a second pattern can be imaged next to the first pattern before etching the underlying layers. Probably all methods for double exposure technology will be used at the 32nm node, as the industry optimizes the process for each chip layer.

Figure 1: ASML’s new Mag-lev stage. (Source: van de Mast/ASML)

ASML, Canon, and Nikon also announced new platforms that will provide the very tight overlay required by double patterning. ASML’s NXT platform [Figure 1] will stay with its two-stage design, but can now move each stage directly using mag-lev technology, a change that reduces the stage mass 67%. By increasing stage acceleration and shortening overhead time, ASML plans to reach 175 wafer/hour (wph). The stage metrology is also new [Figure 2], now referenced to gratings mounted on a metrology frame at the bottom of the main lens. By shortening the air path, overlay errors have been significantly improved, less than 2.0nm (mean + 3σ)

Figure 2: ASML’s new grating based stage metrology. (Source: van de Mast/ASML)

Nikon will stay with a single stage, with first priority to reduce overlay errors. The new Nikon platform uses a hybrid metrology approach. Gratings on the stage around the wafer can be referenced to a metrology frame at the bottom of the projection lens. Stage interferometers will be retained to speed system calibration. Five alignment and focus sensors at an alignment location will shorten alignment time and gather more data during alignment. The stage will scan the wafer under these sensors in a single pass so multiple alignment and focus data can be gathered quickly. Targeted throughput is 200wph.

Optical lithography systems cannot move to higher numerical aperture (NA) lenses. Schott’s latest attempt to make improved high-index lens material failed and the project has been stopped. Optical scanners will have to work with the NA=1.35 lenses that they have now. This makes the push of optics to 22nm even more dependent on process tricks and computational lithography. Design choices will be even more limited. Will there be enough optical process window for production at the 22nm node?

Line-width roughness (LWR) is another serious issue. ASML presented a detailed analysis of excimer laser-induced speckle. Only about 30% of LWR can be attributed to this source. The statistics of photo-acid generation in chemically amplified resists remains the number one challenge.

The EUV story

Full-field (26 × 33mm) EUV scanners are operating at SEMATECH and IMEC (both ASML) and at SELETE (Nikon). SEMATECH reported its alpha demo tool has been operating for nine months. A source upgrade has boosted the pace of experiments. So far IMEC has seen no decay in the transmission of the projection optics — resist outgassing and general vacuum contamination were anticipated problems. SEMATECH reported that by adjusting slit uniformity, CD uniformity was brought into spec. Output is about 4wph, but many sites are not being exposed on test wafers, so real output may still be about 1wph. Nikon’s EUV-1 at SELETE has just begun resist experiments.

Figure 3: Comparison of image quality, 193i vs. EUV. (Photos courtesy of Gil Vandentop of Intel)

EUV images look great — clearly better than comparable 193i images [Figure 3]. Process windows also are significantly better [Figure 4]. 90% of mask defects are not printing, a much better result than predicted. Flare has been measured at 12% to 17% on the three alpha tools, mostly measurement uncertainty; EDA software can correct for flare, which will be reduced to 5%-8% on EUV production tools. Some rule-based OPC has been tried; off-axis illumination and model based OPC probably will be needed for the 22nm node. In general, though, mask design and process control will be much simpler for EUV single exposures with a k1 = 0.50.

Mix-and-match overlay with 193i tools does not yet meet the goal for a single-exposure process at 22nm. But in general, problems are not expected — toolmakers clearly understand how to push the overlay learning curve.

Figure 4: EUV has a much larger process window. (Source: Meiling/ASML)

Nearly all infrastructure items appear ready for EUV. Metrology to build, assemble, and test EUV lenses is ready at all three suppliers. EDA tools needed to make EUV mask adjustments (CD and overlay) and OPC adjustments are available, though process models are not done — resist choices need to be made, and the first production tools are needed. Mask blanks are available; at-wavelength defect inspection of blanks is being developed at SELETE. E-beam patterning of masks is ready. An at-wavelength AIM tool is being developed at Lawrence Berkeley National Labs to determine which mask defects print. One key EUV infrastructure tool is missing: a KLA-Tencor type of tool for scanning patterned masks at high speed and identifying potential defects. Intel says this could be showstopper.

For throughput, another major concern, the picture should improve dramatically over the next 12 months. ASML plans to have its first Gen1 tool installed by mid-2010: a 0.25NA tool with 60wph throughput, upgradable to 100wph as source output increases from 100W to 200W at the intermediate focus. A 10mJ/cm2 resist is assumed. ASML’s plans depend on Cymer’s progress; the supplier reported that factory acceptance testing of its first production LPP source is scheduled for March 2009. Its test platform has reached 40W average power, using a 400 msec (one field) burst and a 40% duty cycle. This should be ramped to 100W average power by the middle of 2009. Cymer will continue to push up the power of its LPP sources to 400W at the intermediate focus. The increased power will provide 175wph using 15mJ/cm2 resist, scheduled for 2012 installations.

Yet another problem area is resist. Gil Vandentop described Intel’s work to screen over 250 EUV resist formulations. Most of this work was done for 32nm half-pitch; they are now shifting to 22nm. Intel has found that an added rinse after post-exposure bake can smooth line edges and clear spaces; an under layer is recommended. Sensitivity can be as good as 8mJ/cm2, though line-edge roughness [LER] needs to be reduced 2X; resist sensitivity in other talks ranged from 9mJ/cm2 to 48mJ/cm2. EUV cost models should anticipate only slower resists will be available in 2011.

The team at Berkeley Labs has determined some LER is caused by EUV mask mirror roughness, which introduces small phase errors. When out of focus, 60%-80% of LER could come from this problem. At best focus a portion of the LER probably comes from absorber edge roughness. The absorber contribution remains to be determined.

Lawrence Berkeley National Labs is upgrading its micro-exposure tool to 0.30 NA, with simultaneous improvements to beam uniformity and off-axis illumination capability. This tool may be the best location to test resists for the 22nm node.

Seth Kruger of the U. at Albany introduced the concept of an acid amplifier for chemically amplified resists. The idea is to have photon-generated acid react chemically with a new resist component to add acid molecules [Figure 5] and make the resist more sensitive. But speed is not the goal — instead, more quencher will be added to shorten the diffusion length. The combination should improve PAG statistics and produce smoother lines. More work is needed to see if shelf life and production goals can be met.

Figure 5: Chemically amplified resist (CAAR) concept. (Source: Kruger/Brainard, U. at Albany)

Some evidence suggests that out-of-band radiation may be degrading full -field images. EUV resists are being adopted from 193nm and 248nm resists. They are sensitive at these longer wavelengths. At present, there is no filter in EUV systems to block this light. Modified mirror coatings or a thin-film window may have to be added to fix this problem. Expect a 2X reduction of light through the system. As an offsetting factor, the lens coating process continues to improve, centering the reflectivity at 13.5nm. A gain of 2X is expected. These two trends should offset each other.

Even if EUV can be ready in time (Gen 1 units in 2010, Gen 2 units in 2011), will they be economical? ASML, Nikon, and SEMATECH have presented separate analyses, all showing the same general picture [Figure 6] that EUV will be cheaper than 193i using double exposure at the 22nm node. This is true even when an $89 million price is assumed for the EUV tool (vs. $52 million for the 193i tool), EUV output is only 100wph vs. 200wph for the optical tools, and mask blanks cost $60K for EUV vs. $3K-$5K for optical mask blanks.

SEMATECH’s analysis looked at breakeven points for throughput and uptime, calculating that initially 40-70wph and 70% uptime will be sufficient; by 2011 EUV tools are expected to do much better than this. The SEMATECH model looks at a range of assumptions for double exposure technology, mask cost, and prints per mask. At 20,000 prints per mask the EUV lead is clear; at 1000 prints per mask the EUV solution costs very little more than today’s 45nm half-pitch single exposure processes. Mask cost is the most important issue. Yields were assumed to be equal for either kind of tool; but data shows a significantly larger process window for EUV single exposure tools. So the yield outcome probably favors EUV.

Figure 6: SEMATECH cost-of-ownership model results. (Source: Wüest/Hughes, SEMATECH)

Will the finish line move?

Nobody will openly discuss the possibility of a delay to the 22nm node — Intel even said they would not delay — but several issues might hold things up. Resist, which has been a problem for 193nm immersion, looks to be a common problem for 13.5nm EUV as well, and may not be ready in 2011 for the 22nm node. Existing optical scanners have demonstrated good 30nm line-space resolution with a useful process window. The EUV alpha demo tools have demonstrated 27nm line-space resolution with a useful process window. At this time, neither technology has been able to push line-space images to 22nm. Line-width roughness is clearly a challenge for both technologies. Details have been discussed already. We may see an intermediate node around 27nm as people hedge and wait for EUV.

DRAM companies talked about launching the 22nm half-pitch node in 2011 with 193i tools, then switching to EUV tools for first via and metal-1 layers as soon as possible. In this scenario, space could be planned in the fab for two or more EUV tools. 193i tools can be used to start production, and then be shifted to less critical layers as EUV production tools arrive. Of course, the current economic crisis (Great Depression 2.0?) may force changes none of us have seen in prior downturns.

As I left the SPIE conference I was asked, “Why did SEMATECH move to Albany?” My answer was, half kidding, ‘It’s the money.’ But then I paused on some observations: the EUV mask program moved to Albany a few years ago; the EUV alpha demo tool is there now; and a full pilot line has been built in Albany to test EUV on real chips at the 22nm node. Last year AMD went to Albany to make the first metal layer on a 45nm chip using EUV (and the chip worked). Even SEMATECH’s press staff has moved to Albany. Clearly SEMATECH has moved to EUV; this could be symbolic. Will the IC industry follow them to EUV? We won’t know for sure until 2011. But this is clearly a close race with EUV closing on the incumbent optical lithography. Any delay of the 22nm node will help EUV. — G.R.


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