By Hans Hirscher, Ph.D. and Hans Auer, Oerlikon Systems
The demand for thin and ultrathin semiconductor devices grows continuously. Discrete and bipolar IC’s as well as devices for stacking or thin packages require thinner and thinner wafers. The challenge is to find a reliable processing method.
Not all thin wafer applications need backside processing. Some devices are ready for singulation when backgrinding is finished. It is only necessary for mechanical flexibility or minimized thickness for high package density. However, backside metallization is needed to manufacture ASICs, power devices, all types of mixed signal devices (e.g. BCD technology), microprocessors and other high-performance logic such as advanced DSP’s, as well as backside contacts in die stacking — all on increasingly thinner wafers.
The main applications for backside metallization (BSM) are:
Backside processing begins with thin wafer handling, and the often-required edge handling on an ever shrinking width; the wafer must not be touched anywhere in the active frontside area. Especially with increasing wafer diameters, the transition from conventional batch processing to automated single wafer processing is a must. Manual thin wafer handling is a critical factor for breakage and reduced yield. Some process steps that addess these issues are available on Oerlikon’s CLUSTERLINE single wafer cluster tool. These include wafer degas, in-situ pre-etch, active thermal management, stress control, improved film performance and wafer cooling.
When thin wafers below a certain critical thickness need to be processed, a wafer support system is required. However, these wafer support systems pose challenges to the backside processing since most of the time organic materials that require lower temperature limits are involved, and are often critical in when used in conjunction with high vacuum processes.
Typical Applications and Processes/Layer Stack Function
For backside metallization of discrete devices, the typical layer stack consists of
three to four metal layers:
To assure good ohmic contact, a deposition at elevated temperature ( T> 300°C ) is necessary to form interdiffusion or alloying with the silicon. The remaining three metal layers should be deposited at low temperature to avoid film stress and excessive bow to the wafer.
Backside metallization to form a solder contact for an improved temperature drain is also a 3 metal system such as Ti- NiV- Ag.
UBM or RDL for chip stacking typically consists of a Ti or TiW adhesion layer followed by Cu or Al as the conductive layer while some metal systems also employ 3 or more materials like Ti- NiV- Cu.
Existing Wafer Support Systems
The thinner the Si wafers are, the more flexible they are. Additionally, reducing the thickness also reduces the mass, which includes thermal mass. Consequently, temperature variations that occur during processing increase similarly.
Several design solutions exist for wafer support systems (WSS). For example, mobile electrostatic carriers provide a glue-free method that replaces tape bonding/debonding with a charging decharging tool. Another uses a glass disc as a rigid carrier. The wafer is bonded to the glass by two layers of adhesive and a release layer. One wafer carrier solution uses a standard or slightly thinned wafer as a carrier with an adhesive layer. Separation is achieved by thermal release. A robust wafer carrier solution uses a rigid outer ring to keep a thin wafer rigid enough for handling and processing. Only the inner area of the wafer is thinned, leaving a stiff outer ring. And finally, the traditional tape carrier involves a “foil” type procedure uses a (standard) back grinding tape for handling and processing. Beyond those mentioned here, a number of specific designs developed for individual needs exist.
There are pro’s and con’s that weigh differently for different applications to each of them. There does not seem to be a “one for all” solution nor an established standard. As the thin wafers undergo different process steps different specific carriers are needed. Even with the transportable ESC carrier method individual carriers are needed depending on the process (back grinding, implantation, wet etch for stress relief, back side metallization).
The CLUSTERLINE platform (Figure 1) handles and processes bare thin wafers as well as wafers on carriers. Following a wafer through the tool, the different handling steps start in the wafer cassette. Wafers are carefully positioned, then mapped (located) in the load lock. Mapping is an especially critical step with thin wafers that tend to bow, and therefore require a specifically design mapping device.
The robot end effector picks a wafer from the cassette, positions it onto the aligner, and then to the next process chamber. The wafer is then elevated to and from the process position by the chuck. Specific sensors assure that a wafer is safely positioned on the lift pins before being picked by the end effector, avoiding a potential wafer breakage. As the wafer is transported from chamber to chamber, its alignment is rechecked by sensors and corrected before placement in the next module. These elements combine to reliably handle thin wafers while bonding them to organic or glass carriers.
Thermal Management
A four-layer stack is typical for BSM processes. The WSS allows more easy handling of the substrates, but depositing metal layers remains a challenge in regards to thermal load to the substrate. All the presented WSS’s use adhesive interface materials, which reduce the thermal flow to the chuck. The following graphic shows this temperature gradient from the wafer through the WSS into the chuck.
Figure 2 illustrates the situation for the mobile ESC. To improve thermal transfer, backside gas is injected into the interfaces. Adding up individual thermal resistivities, you find an effective heat transfer coefficient for the whole system. The delta in temperature across the WSS results in T = 106°C by applying an incoming power load of 0.5 W/cm2.
Compared to a wafer support system that uses adhesives or tape, k-values are comparable (100 and more). There is an unknown factor in the thermal conductivity of these plastic materials (including adhesives). In addition, it’s critical to properly apply these foils. In case of surface topography, which is common on the wafer frontside, the adhesive and tape may not enclose it completely. Temperature and vacuum conditions may generate bubbles and thus partially delaminate the foil which leads to hot spots on the wafer. Consequently, the thermal management in depositing film layers is an essentially important task. Oerlikon has developed a unique in-situ temperature measurement system that uses an optical fiber to look at the wafer backside through a window in the chuck. This allows total control of the wafer temperature during processing for development purposes, as well as temperature monitoring in production (Figure 3).
Conclusion
This single wafer cluster tool offers metallization of thin wafers down to a minimal thickness of approx. 100µm for 200mm wafers and a bow of 4mm. For 150mm wafers, the limit lies at approx. 70µm. When thinner wafers need to be processed, a wafer support system allows for backside. Special care must be taken for thermal management during sputter deposition forming the backside metal layer stack. In combination with the unique in-situ temperature measurement system such supported thin wafers can be run safely and reliably.
Hans Hirscher, Ph. D. process engineering scientist, and Hans Auer, product marketing manager PVD, may be contacted at Oerlikon Systems, Balzers, Liechtenstein. www.oerlikon.com.