Synopsys’ new DFM strategy: Focus on in-design verification

by Debra Vogler, senior technical editor, Solid State Technology

May 14, 2009 – Synopsys Inc.’s just-released IC Validator DRC/LVS for in-design physical verification and signoff for advanced designs at 45nm and below aims to reduce total physical verification time by using in-design verification, stream-out reduction, incremental processing, automatic error detection and fixing, and near-linear scalability across multiple CPU cores. According to the company, the new product is production-ready, having been fully qualified by a leading chip manufacturer for design rule checking/layout verification signoff (DRC/LVS) at the 32/28nm process node.

With this latest announcement, Synopsys is inaugurating a new strategy with respect to DFM. The company’s post-design software tools and yield management and optimization tools will now be referred to as “manufacturing software” or “manufacturing yield solutions,” to differentiate them from what the company considers “true DFM” tools on the design sign of the equation.

The traditional “implement-then-verify” approach to physical verification can result in multiple iterations between design and signoff, notes Saleem Haider, senior director marketing, physical design at Synopsys. At leading-edge nodes, such as 45nm, the conventional method can be slow, and may complicate convergence since layout corrections can alter design objectives such as area, timing, and power. By using what the company calls “in-design physical verification,” full physical verification constraints are brought into the design phase, helping to ensure clean layout upon leaving the design environment and avoiding late-stage surprises close to tapeout. With in-design verification, specific errors and selected areas of layout can be targeted incrementally, providing a speed-up in overall design completion time.

Click here for a video from Synopsys SVP/GM Antun Domic explaining the IC Validator product and strategy.

Design challenges emerging at advanced nodes include many more design rules and increasing design complexity, Haider explained to SST. He thinks a new approach is needed — one that enables high performance and accuracy, “super” scalability, and fast DFM-aware implementation flow. But the biggest emerging need, he said, is for tightly integrated physical design and verification. Using the traditional “implement-then-verify” approach, designers might not find potential problems until much later in the process and more iterations will be needed, he explained. By bringing the manufacturing checks into the design process, i.e., the in-design verification approach, when designers do the final check, only a single pass should be needed. — D.V.


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