The reliability margin of interconnects for advanced memory technologies

G. Beyer, S. Demuynck, M. Stucchi, I. Ciofi, Zs. Tökei, IMEC, Leuven, Belgium

The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures. We posit that for a given supply voltage, the electrical field increases not only by the shrinking half-pitch, but also by the line edge roughness (LER) and the misalignment of vias.

With the continuing aggressive scaling of dimensions and introduction of new materials, the dielectric reliability margin of interconnects in DRAM and Flash memory chips needs to be re-assessed. Line edge roughness and misalignment of vias increase the electrical field between metal wires.

As the half pitch (hp) of the interconnect structures decreases, both the line edge roughness and misalignment of vias need to be reduced. The replacement of tungsten by copper in damascene wires may lead to a loss of lifetime, if residues on top of the dielectric spacing are not well controlled. The lowering of the dielectric constant from 4.2 (silicon oxide) to 3.0 (carbon-doped oxide) does not, however, appear to impact the dielectric lifetime of damascene structures with a dielectric spacing of 40


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