Cadence cutting back on the “M” in DFM

by James Montgomery, News Editor, Solid State Technology

June 11, 2009 – Cadence Design Systems says it is laying off about 5% of its workforce (about 225 full-time positions) and reducing investments in what it calls “the manufacturing side” of design-for-manufacturing (DFM), to save money and narrow its focus to more “critical” areas for customers’ needs.

“The measures we are announcing today streamline our operations as we simultaneously invest to enhance technology leadership in key growth areas,” said president/CEO Lip-Bu Tan, in the statement.

The company described the RIF as described as “resizing the worldwide field organization to current business levels” (a company representative wouldn’t offer specifics on personnel), and decreasing investments in both post-signoff DFM and “other infrastructure areas of the business.” The firm also will shoulder $20M-$25M in pre-tax restructuring charges, $18M of that in 2Q09. The end goal is to save ~$30M in operating costs, while taking into account extra investments that will be continued in “areas of critical importance” such as verification and system-on-chip (SoC).

Editor’s Take:

While 225 lost jobs is inarguably a painful event (and it only takes one to literally bring home the impact), a 5% RIF in most business climates isn’t really startling — and in the current industry/macroeconomic climate it’s actually quite conservative. “This is basically a sales layoff that we’ve been expecting for a few months now,” noted EDA industry guru Gary Smith. He added that the 5% is “way under some estimates” — suggesting that perhaps the company is doing better, faster than expected.

Revenues from Cadence’s DFM product group accounted for only 6% of total company sales; on the one hand that seems a minor loss, on the other hand it’s perhaps a key opportunity lost. A company rep emphasized to SST that “DFM remains a matter of focus for us,” but that the company will now its DFM technology “on the design side, which means we won’t aggressively pursue post-sign off stand-alone DFM opportunities.”

Smith agreed that this could be seen as a necessary move, given “little chance [of] catching up with Mentor or Synopsys” in the DFM-manufacturing arena. But from a longer-term strategic view he sees a big problem. “DFM capability is becoming integrated with a majority of the back-end toolset,” he explained to SST; routers for 65nm and below are all DFM-capable. “This is where Cadence has really been losing ground. Both Mentor and Synopsys have recently been successful in outsourcing some design tool research from the semiconductor vendors,” specifically Mentor, he pointed out. “Without this leading-edge DFM knowledge, it will be highly improbable that Cadence can regain the technical lead in ASIC layout, DRC, and soon custom layout,” which together (plus DFM tools) make up the majority of business in the IC CAD market, he said. — J.M.


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