by Li-Shun Wang, Ana Hunter, Samsung Semiconductor, Inc.; Seung-Mahn Lee, Samsung Electronics Co.
June 26, 2009 – As IC design, manufacturing costs and complexities continue to increase, collaboration with customers from the earliest stages of technology development through high volume production is vital for the next generation foundries. In the earliest stage, collaboration with customers establishes specification, feature definition and process technology requirement. By co-optimizing physical design with manufacturing process technology, foundries can preserve design intent in actual silicon and ensure rapid time-to-market and right-the-first time working designs. During the product and technology development stage, strong partnership in data sharing and FA collaboration enable accelerated yield learning cycles.
To sustain requisite yield, manufacturing process control and defect performance has to be significantly improved. Manufacturing innovation becomes essential for the next generation foundries to keep pace with the scaling advantages of high-k metal gate (HK+MG) in 32nm node and beyond. Process variation in smaller geometry is becoming a pronounced engineering and manufacturing challenge. In this article, we will discuss the advancements in advanced manufacturing using Samsung’s S1 fab, a state-of-the-art 300mm foundry line, as an example in the areas of patterning and closed loop variation control systems.
Leading foundries are moving towards 32nm high-k metal gate (HK+MG) and beyond today. The introduction of HK+MG in the 32nm node though the Common Platform technology alliance, a collaboration among IBM, Chartered and Samsung, offers major benefits of high performance, reduced static and dynamic power . The advanced technology node delivers the expected Moore’s law benefits of increased density and performance and also requires significant investment from both chip design and manufacturing. For HW/SW design in an advanced technology design project, the non-recurring engineering (NRE) cost could go up from $120M in 45nm node to $180M in 32/28nm node . With these development costs, the need for close collaboration and a fast ramp to volume production is imperative for return-on-investment (ROI) for both the customer and the foundry.
Today’s complicated designs and advanced technologies dictate the need for close collaboration between the customer and the foundry. Manufacturing variations can affect device performance and conversely, design layout can greatly impact process variations. Manufacturability of advanced technology is determined by both the design and the manufacturing process. Controlling these factors requires close customer collaboration, new manufacturing methods, and possibly new product design architectures.
Foundry and customer collaboration from the earliest stages of technology development through high-volume production is crucial to success. From the outset, collaboration with customers between design and process technology establishes specification and feature definition. As design rules for each new node change, design-for-manufacturing (DFM) methodology has to improve for continued scaling. Understanding the delta between design intent and silicon results leads to co-optimization of physical design and process technology and thus drives DFM improvement to ensure right-the-first time working design. During the product and technology development stage, a strong partnership in data sharing and failure analysis (FA) collaboration accelerates yield learning cycles.
Yield improvement requires the control of both design marginality and process defects including random, systematic, and parametric defects. Each category contains various issues that the foundries and chip designers must work together to resolve. Fast yield ramp and world class quality can only be achieved with a strong technical relationship between customers and foundries to take advantage of the combined expertise in manufacturing, design and test.
To sustain requisite yield from generation-to-generation, manufacturing process control and defect performance has to be significantly improved. Manufacturing innovation becomes essential for next generation foundries to keep pace with the scaling advantages of HK+MG at the 32nm node and beyond. Lithography, for example, is a significant challenge in semiconductor manufacturing as the device features are well below the most advanced manufacturing worthy lithography tool optical wavelength (Table 1).
Semiconductor Manufacturing Roadmap by ITRS 2007.
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Physical gate length in logic circuits today is getting down to <30nm level requiring 3σ variation control of <2nm. At these geometries, variability in the manufacturing process has a much greater impact on device operation than in previous technology nodes. Variation control and containing systematic and parametric defects is a pronounced engineering and manufacturing challenge. This article looks at the advancements in next generation manufacturing using Samsung's S1 fab (Fig. 1), a state-of-the-art 300mm foundry line, as an example in the areas of patterning and closed-loop variation control systems implementation.
Figure 1. Inside Samsung’s 300mm logic process facility, S1 Line, located on a 350-acre site in Giheung, South Korea.
Early customer collaboration brings significant advantages
The early engagement between device and process engineers and chip designers offers significant advantages to both the foundry and the customer. Customers gain access to the latest technology enabling higher performance, lower power and increased SOC integration with time-to-market advantage. The foundry gets real product design feedback to validate and fine-tune the technology and faster time-to-volume, accelerating ROI. . Without early customer collaboration, the foundry works serially on process unit development, process flow, and specifications. Once these are established, the foundry delivers its design rules and models to the customer. The customer designs a new product and then delivers the design database to the foundry. In this scenario, problems are addressed at a late stage in the flow, whereas it would be much more effective to identify the issues upstream to avoid design delay or respin.
Under close customer collaboration, using a concurrent and interactive work flow, the foundry and customer co-optimize the design and process early in the development cycle through detailed discussions on interaction between process, layout structures and circuit design. The customer provides direct feedback and has significant influence on the manufacturing design rules and technology offerings.
The early collaboration across process and design ensures a better understanding and balance of all requirements to establish the technology specification and feature definition. With this feedback mechanism in place, the foundry provides multiple Vt core transistors, I/O transistors, and SRAM options for size, speed and power trade-offs best suited to designs requiring the latest advances in process technology. The customer can analyze design trade-offs and select the best strategy for the silicon process and design methodology to achieve the product goal within the required power consumption budget and with the best possible performance.
Figure 2 shows the design-process collaborative flow between the customer and the foundry. As result of close collaboration, the customer and the foundry arrive at a set of design rules and silicon options with built in optimization that meet both advanced process and design requirements.
Figure 2. The design-process collaborative flow between customer and foundry.
Accelerating yield learning cycles with data sharing, failure analysis collaboration
Historically, foundries have driven yield improvement by controlling particles from the process tools and environment, manufacturing process flow management and use of statistical process control (SPC). Today, more and more yield-loss issues are related to systematic design and process interaction marginalities. Improving product yield requires both product design tuning and process technology improvement. The design tuning is conducted via the early collaboration described above. Once the design is completed, to achieve stable volume yields, further process tuning requires design topology information input.
An understanding of the device’s physical and electrical characteristics, such as areas of high density features, critical speed paths and the location of precision analog blocks are used to create measurement recipes and fed into inspection systems. The customer and foundry work together to characterize nonfunctioning units and perform physical failure analysis (FA) to determine causes of yield loss, which is then fed to foundry for yield improvement activity. By partnering with the customer to share wafer-level bit map from device functional testing, the foundry can compare wafer-level bit maps to inline inspection results driving a better understanding of failure modes and root cause fixes. Failure bins classification from the functional testing analysis delivered in a real-time feedback path from the customer to the foundry is a key success element for a close customer collaboration strategy. Data sharing and FA collaboration offer high-level diagnostics, which enables accelerated yield learning cycles throughout the product development stage.
To improve yield from the development stage to a mature production level, the foundry must control random and systematic defects and parametric issues quickly. The speed of yield learning goes straight to the business’ bottom line. Random defects are mostly controlled by managing process tools and production environment cleanliness. Systematic and parametric defects control requires both design optimization and manufacturing innovation. The next section discusses the manufacturing advancements in gate patterning and closed loop variation control in Samsung’s S1 foundry line in addressing systematic and parametric defects.
Manufacturing innovation keeps pace with 32nm HK+MG and beyond
With the aggressive scaling of devices made possible with 32nm HK+MG, the required gate CD control comes down to the level of 1-2nm in 3σ. Even with the latest 193nm and 1.35 numerical-aperture (NA) immersion lithography tools, the mask and lithography processes are pushed to the extreme to meet this tight variation control. One option is double patterning whereby very dense tight pitch structures are divided onto two separate masks and “double” exposed. This is not desirable due to the negative impact on cost and throughput. In order to maintain single exposure, novel methods for lithography and etch variation control are required. As an example, Samsung uses a ASML DoseMapper to improve gate patterning quality in its S1 logic foundry fab.
Equipped with DoseMapper capability, ASML lithography tools modulate the exposure dose across the exposure field for process quality enhancement. DoseMapper, if applied correctly, can improve lithographic quality by compensating for external sources of CD variation such as reticle non-uniformity. The manufacturing process for reticles often creates a systematic feature size variation across the reticle field. Using DoseMapper, the dose profile is optimized to compensate for the reticle induced feature size variation in both the slit and scan axes. This technique has been studied in Samsung’s S1 manufacturing process to improve lithography process and systematically improves production quality. For gate patterning, poly interfield variation (AWLV) and process Cpk have been improved by >25% by using DoseMapper as shown in Fig. 3.
Figure 3. Inline parametric Cpk improved by >25% after using DoseMapper in gate patterning.
Closed-loop variation control: design, manufacturing, final test
Process variation is a pronounced engineering and manufacturing challenge today. The application of advanced process control (APC) has been dramatically increased in recent years as the most effective methodology to reduce variation in next generation foundries. Closed-loop variation control systems incorporating APC have been applied from design through manufacturing to final test in semiconductor manufacturing. In Samsung’s S1 fab, more than 100 unit processes are now fully covered and controlled in real time by framework based APC systems.
Although the implementation of APC algorithms requires in depth process and equipment understanding and characterization, the concept is simply how to feed back and/or feed forward the previous lot/wafer’s data to current and/or future lot/wafer to reduce the cumulative variation effects of each process step while maintaining the process feature at the specification target. To design an APC model, the APC team has to determine that it is controlled by each process, each chamber, each recipe, each product, etc, which is decided based on the communication with process and device teams. In Samsung’s S1 fab, APC systems are now in effect for almost all film processes and have demonstrated Cp and Cpk improvement by more than 25% in actual product data.
The lithography processes, key etch and implant processes are controlled by an APC system and the control performance shows similar improvements in ADICD, ACICD and related electrical testing (ET) data. Figure 4 shows the control performance of gate loop APC system on related key ET data. The Cp was improved by 40% by use of APC in the gate module. Advanced tool features such as the ASML DoseMapper that can adjust exposure dose in response to APC information from the reticle and etching process are making it possible to attain high yields in spite of the technical challenges at 32nm and below.
Figure 4. The implementation of closed loop control at gate loop showed >40% Cp improvement in key electrical testing data.
With today’s escalated development costs and complicated chip manufacturing, the need for close collaboration and a fast ramp to volume production is imperative for ROI for both the customer and the foundry. By partnering with the foundry, the customer achieves early understanding of the new process technology, which translates to fast time to market and superior product design with built-in process optimization and proven foundry technology. In addition, manufacturing innovation in 32nm HK+MG technology and beyond will continue to bridge the gap down to the process technology roadmap by containing both process variations and manufacturing defects to sustain requisite yield for the next generation foundries.
The authors would like to thank Dr. Steve Hah and Moon Won Lee of Samsung’s S1 fab, Dr. CS Choi of Samsung Foundry, Dr. Insik Chin of System Engineering Group in SEC, and Lisa Warren-Plungy of Samsung Semiconductor, Inc. for their support and contribution to this article.
- K. M. Choi, “Advantage of 32nm High-K & Metal Gate: Design & Product Perspective,” Common Platform Technology Forum, San Jose, CA 2008.
- M. Keating, “Reshaping Chip Design — From Architecture to Tapeout,” SNUG San Jose, CA 2009.
- Y.H. Su et al., “Inter-firm Collaboration Mechanism in Process Development and Product Design between Foundry and Fabless Design House,” Semiconductor Manufacturing Technology Workshop Proceedings, pp. 47-50, 2004.
Li-Shun Wang received a PhD in materials science and engineering from Northwestern U., and a BS in physics from the U. of Science and Technology of China. He is a foundry engineering manager at Samsung Semiconductor, Inc (SSI) in San Jose, CA. E-mail: [email protected]
Seung-Mahn Lee has a PhD in materials science and engineering from the U. of Florida and is a principal engineer at Samsung, S1 fab, Samsung Electronics, Giheung, Korea.
Ana Hunter serves on the GSA board of directors and is VP of foundry in Samsung Semiconductor, Inc (SSI) in San Jose, CA.