by Michael A. Fury, Techcet Group
June 1, 2009 -For most of the symposia, Thursday (May 28) was the last day of the meeting, which saw the continuation of symposia on flexible electronics, emerging dielectrics, SOI and graphene, among others. The actual final day, Friday May 29, was all about battery/energy and SOI tech (more on that later).
[A reminder: the complete ECS Spring 2009 abstract directory can be found here.]
D. Scott of U Hawaii showed some early work on a novel fuel cell that harvests energy directly from simple monosaccharides without the use of membranes, precious metal catalysts, enzymes or microorganisms [symposium/abstract ID: B4-367]. The design is based on off-the-shelf components including high surface area carbon electrodes and organic dyes in alkaline solution.
A. Kannan of ASU led collaborators from Toronto, Boston, and Warsaw, Poland in a novel effort in bio-fuel cell design involving the immobilization of glucose oxidase on multi-walled carbon nanotubes [B7-514]. With an improved method for achieving a higher level of GOx clustering on the MWCNT substrate, a power density of 55μW/cm2 was demonstrated.
Some successes in fabricating sub-100nm pitch patterns in low-k dielectrics for damascene interconnects [E4-769] was shown by C. Labelle of AMD and a team from Applied Materials working at Albany Nanotech. Pattern collapse of the dielectric is an issue that, like photoresist, can be the result of exposure to wet chemical processing and surface tension effects, but dielectric collapse was also observed without wet chemical exposure when the aspect ratio exceeded a critical limit. The critical dimension process window for avoiding collapse was an exceedingly narrow 8nm.
P. Joshi of Sharp Labs presented a sweet spot for depositing high-performance SiO2 gate dielectric by high-density PECVD at 100°-300°C for TFT fabrication on low-temperature flexible substrates [E4-776]. The resulting films compared favorably with TFT gate dielectrics from higher temperature processes.
K. Nagata of JASRI in Japan, in collaboration with TEL, showed a novel post-deposition microwave plasma treatment for densifying 450°C CVD SiO2 films to bring the film density, electrical properties, and stress more in line with 900°C CVD and thermal oxide films [E4-777]. Dramatic improvement was observed in the low temperature oxide film, though electrical testing in device structures remains to be done.
C. Hwang of Seoul National University presented his DRAM gate stack work using a rutile TiO2 dielectric (k~100) lightly doped with Al to mitigate leakage current at the extremely thin EOT target of tox~0.4nm [E5-830]. The metal gate was a thin Ru/TiN bilayer, although a case was made for improving the dielectric performance by using a RuO2 gate instead.
O. Tonomura of Hitachi showed a new capacitor structure for ≤40nm DRAM [E5-839] that avoids the >800°C anneal usually required to obtain rutile TiO2 by growing the TiO2 on RuO2, for which rutile is the native form. Fabrication was done starting with a Ru bottom electrode and growing the TiO2 dielectric on the native RuO2 film, without an explicit Ru oxidation step being necessary. To suppress leakage current, the TiO2 was lightly doped with 0.3% to 0.8% Co (k~90).
D.-S. Chen of National Chung Hsing University in Taiwan presented a kitchen-sink approach to a nitride diffusion barrier for <45nm copper interconnects [E5-840]. The 40nm thick barrier film was a reactively sputtered nanocomposite of AlCrTaTiZr-nitride in equimolar ratios, a class known as a high-entropy-alloy nitride (HEAN) materials. The resulting barrier was nanocrystalline in the range of only a few nanometers, with no evidence of crystal growth, silicide formation or copper diffusion at annealing temperatures as high as 900°C.
A. Smirnova of U Conn used supercritical CO2 to disperse and deposit organometallic catalyst precursors in a nanostructured carbon aerogel [I6-1464] for use in proton exchange membrane fuel cells (PEMFC). The aerogel had an average pore size of 9nm and surface area of 550m2/gm, making scCO2 an ideal carrier fluid. The pre-catalyzed aerogel was sintered at 700°-900°C to reduce the precursors to metals that included Pt, Co, and alloys with Ir. Electrochemical testing showed an extremely high activity level, particularly for the PtIrCo alloy, that was attributed to the very high dispersion level achieved with the scCO2 deposition method.
ECS Day 5: Battery, energy, SOI
While for many the ECS show ended on Thursday, both Thursday Friday encompassed a Battery/Energy Technology Joint General Session and SOI Device Technology symposia, an indication of the global breadth of research interest and funding in these fields.
K. Kotaich of OnTo Technology LLC demonstrated a viable pathway for recycling spent lithium ion batteries as a source of raw materials for electric vehicle power [B1-221]. The lithium iron phosphate cells are reprocessed with a proprietary (of course!) method that produces material with nearly the theoretical level of specific capacitance. This proposed pathway is among a very small number of options available today for spent lithium ion batteries, of which over two billion are manufactured annually. It remains to be seen whether this supply chain can provide enough material to the EV industry to make a significant dent, but the efforts are still young.
C. Patrissi of the U.S. Naval Undersea Warfare Center showed a clever prototype lithium-sea water battery [B1-238] capable of surviving underwater at 70 psig as the lithium electrode is consumed and the battery cell collapses. The enabling technology is a water impermeable ceramic electrolyte with high Li-ion conductivity. The Li anode is placed inside a collapsible impermeable pouch with a 250μm thick ceramic electrolyte window, thus avoiding contact of the sea water with the lithium and all of the associated corrosion issues. Early results show 96% Li utilization in a continuous discharge test of 550 hours. This suggests that it may be possible to capture the extremely high theoretical energy density of lithium, 8522 Wh per kg.
F. Balestra of the Sinano Institute in Grenoble made a case for the use of SOI as the platform of choice for devices beyond 32nm [E9-950]. Representative application examples were cited for low power, high performance, high frequency, multi-gate and memory devices. The beneficial concepts of strained channels can be extended to strained SOI. Floating body DRAM cells that do not require a capacitor have been demonstrated.
S. O’uchi of the Nanoelectronics Research Institute in Tsukuba, Japan presented his work on a FinFET SRAM device with superior noise stability for both read and write operations [E9-963]. Called a Flex-Pass-Gate SRAM, the device exhibits a peak 320mV noise margin in read operations, compared to a peak 200mV for planar bulk devices. Similarly, in write operations, the Flex-PG device has a peak 350mV margin compared to 210mv for bulk planar devices. The SRAM cell was designed using both 3 terminal and 4 terminal FinFET devices.
Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; email [email protected].