Toshiba touts Ge interlayer for 16nm LSIs

June 15, 2009 – Toshiba says it has devised a gate stack with an added strontium germanium (SrGex) interlayer to achieve the high carrier mobility required for 16nm LSIs, overcoming what it says are twin challenges of fabricating a thin gate stack while maintaining high hole mobility.

Silicon metal-insulator-semiconductor field-effect transistors (MISFETs) are approaching physical limitations to obtain sufficient drive currents at smaller nodes, the company explained in a statement. Germanium (Ge) is a known alternative with higher carrier mobility characteristics, but has its own technical challenges including development of gate stack structures; germanium oxide (GeO2) has shown high hole mobility but its low dielectric constant is a problem to reducing EOT to the 0.5nm seen necessary for the 16nm node.

The new work, being presented at this week’s VLSI Symposium in Japan, describes an ultrathin high-k Ge gate stack using SrGex as an interlayer between the insulating layer and germanium channel. After subjecting the germanium to heat surface treatment in an ultrahigh vacuum, a layer of strontium (up to 10 atoms thick) and then a lanthanum aluminate (LaAlO3) high-film are deposited; then the gate stack is annealed in a nitrogen atmosphere. The SrGex layer is formed during these processes between the high-k film and germanium channel.

Cross-section of the new gate stack structure, applicable to Ge-MISFET for 16nm node LSIs and beyond. (Source: Toshiba)

Toshiba says the new structure realizes peak hole mobility of 481 cm2/Vsec, a record for high-k MISFETs, which is over 3× that obtained without the SrGex layer and >2× the universal mobility of silicon based on the same gate field.

The company also said it has formed a gate structure with EOT of ~1nm, and inserting the SrGex interlayer only increased EOT by 0.2nm “at most” — suggesting the EOT could be further scaled to 0.5nm by reducing the thickness of an overlaying high-k layer or adopting a high-k layer with a higher dielectric constant.

Development of the new gate stack process technology was supported by grants from Japan’s New Energy and Industrial Technology Development Organization (NEDO).


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