3D integration: A status report

July 14 — The idea of thinning, stacking and interconnecting chips is not new: suppliers of memory and flash drives have successfully been doing that for years. The difference between the approach they typically use and the 3D integration that has become the buzzword of today is mostly related to how the chip-to-chip connections are made. The traditional approach is with wire bonding, which has many advantages: it uses the installed base of equipment, it’s low cost, and it’s well understood. Two- and four-chip wire-bonded stacks are common today, and stacks with nine or more chips have been produced.

The main problem with wire bonding is that long looping wires can lead to higher levels of resistance, capacitance, and inductance and other electrical performance issues. That’s not a problem for most memories today, but could pose a potential problem in the future and for special applications, such as the integration of memories with microprocessors. Wire bonding on very thin die can also be a challenge in that the force required can sometimes crack or break a die — far from ideal if that die were one of the last die in a multi-chip stack.

An alternative approach, where chips are thinned, stacked, and interconnected with through silicon vias (TSVs) fabricated with front-end-like processes (etch, dielectric deposition, and electroplating) offers great promise as a way to achieve higher levels of functionality in a smaller space, with higher performance and potentially lower cost than wire-bonded chip stacks.

This approach has been the focus of an on-line virtual forum, hosted by public relations firm MCA at www.semineedle.com/MCA3DIC. The panel, moderated by industry commentator Francoise von Trapp, consists of Robert Patti of Tezzaron Semiconductor, a semi-fabless memory supplier, Sitaram Arkalgud of SEMATECH, Paul Linder of EVG, Ricardo Borges of Synopsys, and Jean-Christophe Eloy of Yole Development, a market analyst firm.

One of the main focal points of the forum has been to define exactly where 3D integration is today in terms of industrialization. Patti of Tezzaron said that he is seeing a “huge increase” in customers trying their first 3D devices. “They range from complete test devices which covers a lot previous work in the industry, but allows the customer to get their own data, to very complex 3D logic and memory devices. We expect our customers alone to fabricate more new 3D devices in the next 12 months than all previous work combined. I’m sure that other 3D technology providers are seeing the same industry pull through today,” he said.

Paul Linder, EVG’s chief technology director, said we are at an early stage when looking at industrialization level. “Many pilot lines at manufacturing sites are getting online — a good change from years ago when 3D-IC was mostly a research topic,” he said.

With the exception of early adopters, such as CMOS image sensors, most companies are working on the qualification of specific process integration schemes, Linder added. “All of the new 3D process steps around TSV’s (litho, bonding, thinning, etching, and plating) are well-developed and can benefit from continuous improvement programs already.

“When it comes to process integration we see a lot of diversity out there and proprietary process flows. We think this is typical for revolutionary technologies and enables initially a competitive benefit to our customers. In the long run we expect that standardization will become more attractive to the users.”

The benefits of 3D

One of the clearest benefits of 3D integration, and why it could be quickly adopted into mainstream manufacturing is speed, noted Patti. “Scaling continues to make transistors faster, but wire, as we all know, just gets slower. Physics just conspires against us here. The improvement in transistor performance is tiny compared to the slowdown of the wire. To make wires faster, you need to make them shorter. 3D can do that far better than scaling and at a comparatively small cost,” he said.

3D offers benefits in power, density and cost, but these require new approaches, Patti noted. “Co-mingling of transistors and wire allows process separation leading to reduced costs — i.e., just build memory in the memory process, just build logic in a logic process,” he said. “SOCs put a huge burden on processing. If you need flash, DRAM, and a processor on the same chip, you have a fab nightmare.” The cost burden is huge, he pointed out — even though none of the functionality (flash, DRAM, or CPU) covers the entire chip, “the entire chip gets these processes applied to it. I like to say the foundry does offer a refund for under-utilized silicon area. With 3D, unecessary processing can be avoided, lowering cost and improving yield.”

Another advantage is density: Four layers of 45nm circuitry take about the same space as one 22nm device. “By virtually any measure, development cost, fab facility cost, even piece part, 3D wins.” Patti said.

A third advantage is power. “If we assume high-k gates, and lower transistor leakage, most of the power is left in the charging and discharging of the wire,” Patti said. “Make shorter wires [and] you get lower power. In our memories we make the wires half as long and we get a 40% reduction in per bit power.”

How 3D rescues Moore’s Law

The real advantage of 3D integration, however, is that it offers a way to stay on the path defined by Moore’s law without continued scaling, which is getting increasingly expensive. “I think in the end you need to look at what is the objective of scaling. Historically, it was performance, power, cost, and density. Performance was probably the driver for many years, at least for logic devices,” Patti said. “For DRAM it most certainly was cost. Today, it is safe to say, we get no performance improvement from scaling. Power isn’t improving. 3D can drive density faster than scaling. And the cost benefit from scaling is rapidly eroding. 22nm may be more costly than 45nm per transistor for sometime.”

But don’t get him wrong — he’s not predicting an end to scaling, rather a major slowdown. “Fractional node advances are going to be the norm moving forward. The next decade or two will belong to 3D integration, just as the last has been the domain of CMOS. The exploitation of 3D has barely started. The opportunities go far beyond just connecting together the bond pads,” he said.

Michael Fritze, program manager at DARPA, said he sees 3DIC as a potential means of making affordable SoCs, thus “enabling a whole new range of applications that are simply not economically viable today given the volumes required to justify a custom SOC design.” Fritze is also bullish on the potential of 3DIC for achieving ultralow-power electronics solutions, although he said serious design and architecture changes would be required to achieve this. “This is the key challenge: getting folks to start thinking about the novel architectures that would be capable of exploiting 3D IC benefits. This will require CAD/EDA tools before killer apps are identified — quite an economic challenge,” he noted. — P.S.


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