ASML fulfills “holistic litho” plan with two tools, custom packages

by James Montgomery, news editor, Solid State Technology

July 14, 2009 – Citing the embodiment of its concept of “holistic lithography,” ASML has unwrapped two hardware/software components to help chipmakers improve lithography process windows while avoiding costly and timely steps and maintenance downtime.

Traditional lithography likely faces the end of its road at 1.35NA wavelength, beyond which EUV is likely to take over; until then, chipmakers need to extend their processes as much as they can, explained Bert Koek, ASML’s SVP of lithography applications, in a presentation at SEMICON West. Shrinks reduce manufacturing costs and improve device performance, but they also tighten process windows and restrict production tolerances for parameters such as overlay and critical dimension uniformity (CDU).

The company’s concept of “holistic lithography,” represented by application-specific customizable packages branded under the name “Eclipse,” integrates computational and wafer lithography with process control to optimize process windows and keep the process in a “sweet spot.” Scanner data is pulled into a simulation, using pattern optimization (via Brion’s Tachyon source mask optimization [SMO] software) and verification so that users can “fine-tune” scanner settings and maximize the process window. Metrology techniques and feedback loops monitor overlay and CDU performance to continuously maintain the system centered in the process window. The concept aims to reduce the need for reusing reticles or test wafers, resulting in significant time and cost savings — e.g., the $100k’s in reticles and several weeks to respin. Design verification is known earlier, which reduces design proofs, time to ramp, and improves yields.

ASML’s “holistic lithography” flow. (Source: ASML)
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Asked to quantify how the Eclipse package could translate to extending immersion litho for various devices, Koek suggested that NAND flash could push to 25nm and even 20nm using spacers and 1.35NA; DRAM can get to 3Xnm; and logic to 32nm with single patterning before hitting the 22nm and probably adopting double-patterning.

Two new products flesh out the “holistic litho” concept. FlexRay is a freeform illumination technology that uses a programmable array of thousands of micromirrors, instead of a traditional illuminator and diffraction optical element (DOE), to condition and shape the light with greater flexibility to create increasingly complex patterns. (Koek acknowledged an audience question that ASML’s decade-old “aerial illumination” technology could be considered “an early version” of this.) SMO-defined pupil shapes can be rendered in a matter of minutes (initial setup time is around 10mins) vs. weeks with DOEs, and “an unlimited number” of DOEs can be stored in the scanner. ASML says tool-to-tool OPE matching is improved 50%, with 20% better CDU through pitch.

Koek presented various slides showing improvements by using the freeform illumination shape vs. quadrupole illumination, with depth-of-focus nearly doubled for 4Xnm DRAM and increased >50% for logic.

Mask and freeform source co-optimization improve process window. (Source: ASML)
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Tachyon SMO & FlexRay in a logic contact pattern, resulting in a larger process window and lower mask complexity. (Source: ASML)
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The other new product is BaseLiner, which addresses the problem of parameter drift; when tools stray out of spec the tool needs to be taken out of operation and recalibrated. With BaseLiner, monitor wafers are added to the production sequence, and standard measurements are captured “off-tool” daily by a metrology tool (say, ASML’s YieldStar systems) and exposed using a reticle with special scatterometry marks, to see how far the system has drifted from its “baseline.” Overlay and focus correction sets are then calculated and converted by the Twinscan system into corrections for each exposure on subsequent production wafers. A bonus, ASML says, is if a fab practicing overlay grid matching uses “golden” reference wafers as their baseline for overlay stability control.

(Source: ASML)
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Beta testing for BaseLiner will start in December with orders taken starting in 1Q10, with initial release on Twinscan XT:1700i, 1900i, and 1950i immersion systems on release 4.5. It will be offered by itself or bundled with ASML’s YieldStar tool, BaseLiner server, and BaseLiner reference reticle.

FlexRay will be offered as a factory option on the 1900i, 1950i (XT and NXT) and future systems; beta testing will start in 1Q10 with first products shipping in 2Q10. Toshiba is an early user of the FlexRay freeform illumination shape capability, combined with Brion’s Tachyon LMC and OPC+ for resolution enhancement techniques (RET), to extend its use of immersion lithography to the 2Xnm node. — J.M.

Examples of Eclipse packages. (Source: ASML)
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