Best of West: Going green with DI water clusters

by James Montgomery, news editor, Solid State Technology

July 16, 2009 – Improve a process, save money and eliminate waste, with no loss of performance or efficiency, and go green at the same time. They’re the reasons Nano Green Technology was awarded SEMI’s 2009 Best of West award Wednesday (July 15) at SEMICON West, for its technology that replaces the traditional SC-1 or SC-2 etch-based cleaning process with a megasonics-based solution that relies on water. SST also takes a snapshot of the other Best of West finalists: Alchimer, Gore, IMEC, and K-Patents.

The company’s CCS-1000 (CCS stands for “critical cleaning system”) combines deionized (DI) water with a “slight amount” of ammonia gas as a seed (a $300 Evian-bottle-sized amount lasts a year) to form molecularly-activated clusters (trademarked and branded as IMACS, for “ionized molecularly-activated coherent solution”), which go out and seek charged particles, explained Michael Olesen, manager of applications and technology, in an interview with SST. An SC1 process has to etch through the boundary layer to pry loose particles from the material surface (causing roughening), and during rinse these particles are likely to fan out and reattract and reattach to the surface anyway. The water “clusters” in Nano Green’s DI water solution seek out, attract to, and hold the particles so they can be rinsed away, with no worry about redistribution and reattachment to the surface.

The technology is applicable to any tool platforms for all types of cleaning in batch (RCA, post BOE, pre-sacrificial oxide, pre poly gate, post metal, gate oxide) or single-wafer processing (pre metal etch, poly gate, pre-photoresist, post-CMP, pre diffusion.

The system’s benefits are striking: removal efficiency said to be equal to or better than SC-1 processing, with pre 99.0% for nitride particles (the company showed data to back up claims). There are virtually no chemicals or special handling costs, no loss of topography (no reaction with native oxides), no VOCs or metallic ions, “dramatically” reduced megasonics energy (thanks to the charged clusters), and no waste treatment — in fact, Nano Green president Jacob Mor told SST that customers are encouraged to flush the DI out in the drain where it captures garbage residues there, too. Considering the volumes of scale in a DI-based technology like this (potential 1M gallons/day through a fab), payback can be achieved in as little as five months, he noted.

The company, which first got a thumbs-up from Infineon and IMEC at the 2007 Surface Preparation and Cleaning Conference (SPCC), has five tools in the field, Mor said — one has been qualified and now in use at TSMC; another customer is in qual at 32nm (and later 22nm); another is in final eval at 37nm for final clean and post-CMP; and the company is in final discussions with Intel for use in both its fab and photomask operations. The system is also being explored by a hard-disk drive manufacturer, and a fifth tool is now shipping out in the field to an unidentified end-user. Market spread in the near-term will be ~75% semiconductors, ~15% HDD, and ~10% TFT/LCD. The company is also interested in the PV sector too — where presumably the “green” message will resonate even more strongly — but Mor indicated this won’t happen in the short-term.

Nano Green’s business model is in three phases, Mor explained to SST. Phase one is “industry recognition,” getting installs at handpicked users like Intel and TSMC. Once users are on board, Phase Two is to license the technology to the toolmakers. Phase Three, he said, will be to “build a farm” for end users to offer the technology directly. Once the company builds its valuation to ~$250M, he said (now at ~$12M, with a second funding round about to close), the goals are in the short-term, possible M&A, or longer-term, pursuing an IPO. — J.M.

Nano Green was one of five Best-of-West finalists. The others had compelling stories of their own:

Alchimer, AquiVia. This electrografting technology, which encompasses three process steps before filling a through-silicon via (TSV) with metal, seeks to replace dry steps with wet deposition of insulator, barrier, and copper seed layers in high-aspect ratio TSVs. The technology uses standard plating tools, and is independent of via depth — dry can’t go higher than ~5:1 AR; Alchimer CTO Claudio Truzzi told SST that in-house 18:1 AR has been achieved. It also offers a 10× better tolerance for “scalloping.” Truzzi noted that relative cost-of-ownership benefits for the eG wet process vs. a dry process (on new equipment) can exceed 50%. Next step for Alchimer is to expand the technology beyond its French headquarters to regional “application lab” capabilities. The company is fresh off a $10M round of funding, and is in final negotiations with an anonymous “Top-Tier” manufacturer to utilize their technology.

W.L. Gore, Filters for semiconductor applications. These 20nm-100nm-rated cartridge filters for chemicals, dilute chemicals, and ultrapure water in wet process tools incorporate a new high-flow ePTFE (expanded polytetrafluoroethylene) filtration media, which when rapidly stretched under the right conditions creates a very strong, microporous material with higher void values. It allows a drop-in retention upgrade from 100nm to 30nm, enabling cleaner recirculation baths and reduced processing times. Glowing quotes from a happy end-user shown to SST were a bit over-the-top, but the company showed slide after slide backing up claims with data, showing how replacing a 0.05μm ultrapure water filter with its 20nm ePTFE hydrophilic filter reduced particles by 55%-61% for particles ≥0.05μm and 0.1μm, pressure drop declined >90%, and nonvolatile residue rinse time went from several days to <3hrs.

IMEC, Slim-Cut. This method addresses a top challenge of crystalline Si solar photovoltaics: kerf-free wafering of substrates as thin as 50μm. A metallic layer is screenprinted on top of a thick c-Si wafer and high-temp annealed in a belt furnace; when the wafer cools, the difference in metal/silicon thermal expansion coefficients induces a stress in the substrate, which expands into a crack close to and parallel with the wafer surface. The top layer of Si and attached metal layer snap off, and the metal layer is etched away from the silicon foil, leaving an ultrathin silicon foil — and the remaining substrate can be reused to peel off further layers.

K-Patents, PR-33-S refractometer. This digital refractive index (RI) measurement technology promises to increase wafer throughput and cut down chemical costs from supplies down to fab in-line and tool in-situ chemical concentration control.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.