Double patterning’s 22nm win for breakfast

by Franklin Kalk, chief technology officer, Toppan Photomasks

July 15, 2009- Virtually everyone knows by now that double patterning will bridge the gap between the low k1 limit of single-exposure 193nm immersion litho and the emersion of EUV litho (among others). But which double patterning techniques will do the trick, and which technology cycle will signal the end of the bridge to EUV? Wednesday’s Sokudo Lithography Breakfast gave us a buffet of double patterning views as the transition from single exposure 193i closes in at 40nm half-pitch.

Tom Wallow of GlobalFoundries framed the imaging problem in the context of moving below 80nm pitch in complex logic designs, which corresponds to the 22nm-to-15nm logic transition. He described the use of the litho-freeze-litho-etch (LFLE) process for brightfield gate imaging and darkfield contact imaging, and in the process showed how LFLE strikes a nice balance between process and materials complexities (i.e., track and resist requirements). It’s nice when life works that way.

Nikon’s Stephen Renwich and ASML’s Skip Miller had different takes on meeting the same double patterning image specs with a 200wph scanner. Both showed similar approaches to achieving 2nm overlay and sub-1nm CD accuracy — but then they parted company. Renwich emphasized defect control and the importance of a modular tool architecture in facilitating easy installation and maintenance. Miller, meanwhile, focused on the integration of computational and wafer lithographies to realize double patterning’s potential.

LFLE has many variants, which places tremendous demand on the track. Charles Pieczulewski of Sokudo used three resist manufacturers’ LFLE flows to demonstrate the flexibility required of a modern track that must also run 250wph. Impressive stuff.

For treats, Bob Johnson of Gartner wrapped up the session with an upbeat assessment of the semiconductor industry’s immediate future. Save for the self-destructive overbuilding in memory, the industry has managed inventories and capex very well throughout the downturn and that bodes well for the next several years, Johnson said. Moreover, capex will transition from the recent “mission critical only” spending to new technology investment later this year, followed by capacity adds next year. That impressed the crowd, too.

So the stage is set: 193nm immersion, double patterning, and computational lithography will bridge the EUV readiness gap to at least 22nm logic (and the attendant memory half-pitches). Will EUV defend at 16nm? Will Sokudo’s speaker have a name I can spell? Stay tuned; there’s always next year. — F.K.


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