July 17, 2009 – EV Group and Applied Materials say they will jointly develop wafer bonding processes for making through-silicon vias (TSV) in 3D IC packaging applications, working as members within the Semiconductor 3D Equipment and Materials Consortium (EMC-3D).
Conventional ICs use wafers with ~750μm thickness, but 3D ICs require thinner ones, ~≤100μm, which lose structural and edge integrity in high-temp and high-stress processes such as metallization. EV Group and Applied plan to pursue bonding temporary carrier wafers to device wafers prior to thinning, to support them during subsequent process steps, and be removed afterwards. The work, to be done at Applied’s Maydan Technology Center, will explore using silicon and glass carriers, determining substrate stability using EVG’s wafer bonder and thin-film handling with AMAT’s etch/CVD/PVD/CMP process tools, to come up with “baseline processes and recommendations” for carrier wafer usage; results will be shared with EMC-3D member companies.
“We are excited to collaborate with an industry leader like Applied, to expedite temporary bonding and debonding capabilities for 3D IC development,” said Markus Wimplinger, corporate technology development and IP director at EV Group, in a statement.