July 30, 2009: MOSIS, a prototyping and low-volume circuit production service, is expanding its shuttle runs to include two more of IBM’s silicon-on-insulator (SOI) process technologies, for 0.18μm/200mm wafers and 45nm/300mm wafers.

The 45nm shuttle run, scheduled for Sept. 1, 2009, uses IBM’s 12S0 technology, which offers up to 30% transistor performance improvement over traditional bulk technology at the same lithography node, and can reduce circuit area by up to 25% vs. bulk CMOS. Four transistor options are available (regular, high, super-high, and ultrahigh voltages), and up to 11 metallization layers. A range of options for SRAM, embedded DRAM, and ESD protection and passive elements are available.

The 0.18μm SOI process offers low insertion loss and high isolation, targeted for components such as RF switches that perform the function of on/off devices in wireless applications like cell phones, WiMAX, and wireless LANs. The first shuttle run for the 0.18μm SOI process has already been completed; the next one is scheduled for Sept. 14.

“The 180nm 7RF SOI technology provides a very compelling alternative to GaAS (gallium arsenide) technology for RF switches, while the 45nm SOI technology delivers outstanding performance while maximizing power efficiency and minimizing overall chip size for SoC (system-on-chip) applications,” said Wes Hansford, Deputy Director of MOSIS, in a statement.

For IBM, the expanded service with MOSIS “makes our advanced SOI technology accessible to an even broader array of innovators,” added Regina Darmoni, IBM’s director of analog/mixed signal & digital foundry. “MOSIS provides IBM with additional channels to market, and we are looking forward to this further expansion of our fabrication solutions to enable a new generation of advanced devices and clients.”